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Replace InsertLane format with TernaryImm8

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The InsertLane format has an ordering (`value().imm().value()`) and immediate name (`"lane"`) that make it awkward to use for other instructions. This changes the ordering (`value().value().imm()`) and uses the default name (`"imm"`) throughout the codebase.
This commit is contained in:
Andrew Brown
2020-05-26 13:56:52 -07:00
parent e430984ac4
commit 7d6e94b952
17 changed files with 69 additions and 69 deletions
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8
cranelift/codegen/meta/src/isa/x86/instructions.rs
View File

@@ -342,9 +342,9 @@ pub(crate) fn define(
The lane index, ``Idx``, is an immediate value, not an SSA value. It
must indicate a valid lane index for the type of ``x``.
"#,
&formats.insert_lane,
&formats.ternary_imm8,
)
.operands_in(vec![x, Idx, y])
.operands_in(vec![x, y, Idx])
.operands_out(vec![a]),
);
@@ -369,9 +369,9 @@ pub(crate) fn define(
extracted from and which it is inserted to. This is similar to x86_pinsr but inserts
floats, which are already stored in an XMM register.
"#,
&formats.insert_lane,
&formats.ternary_imm8,
)
.operands_in(vec![x, Idx, y])
.operands_in(vec![x, y, Idx])
.operands_out(vec![a]),
);

8
cranelift/codegen/meta/src/isa/x86/legalize.rs
View File

@@ -460,7 +460,7 @@ fn define_simd(shared: &mut SharedDefinitions, x86_instructions: &InstructionGro
// Move into the lowest 16 bits of an XMM register.
def!(a = scalar_to_vector(x)),
// Insert the value again but in the next lowest 16 bits.
def!(b = insertlane(a, uimm8_one, x)),
def!(b = insertlane(a, x, uimm8_one)),
// No instruction emitted; pretend this is an I32x4 so we can use PSHUFD.
def!(c = raw_bitcast_any16x8_to_i32x4(b)),
// Broadcast the bytes in the XMM register with PSHUFD.
@@ -494,7 +494,7 @@ fn define_simd(shared: &mut SharedDefinitions, x86_instructions: &InstructionGro
// Move into the lowest 64 bits of an XMM register.
def!(a = scalar_to_vector(x)),
// Move into the highest 64 bits of the same XMM register.
def!(y = insertlane(a, uimm8_one, x)),
def!(y = insertlane(a, x, uimm8_one)),
],
);
}
@@ -568,11 +568,11 @@ fn define_simd(shared: &mut SharedDefinitions, x86_instructions: &InstructionGro
// Use scalar operations to shift the first lane.
def!(a = extractlane(x, uimm8_zero)),
def!(b = sshr_scalar_lane0(a, y)),
def!(c = insertlane(x, uimm8_zero, b)),
def!(c = insertlane(x, b, uimm8_zero)),
// Do the same for the second lane.
def!(d = extractlane(x, uimm8_one)),
def!(e = sshr_scalar_lane1(d, y)),
def!(z = insertlane(c, uimm8_one, e)),
def!(z = insertlane(c, e, uimm8_one)),
],
);
}

16
cranelift/codegen/meta/src/isa/x86/recipes.rs
View File

@@ -608,12 +608,12 @@ pub(crate) fn define<'shared>(
// XX /r with FPR ins and outs. A form with a byte immediate.
{
recipes.add_template_inferred(
EncodingRecipeBuilder::new("fa_ib", &formats.insert_lane, 2)
EncodingRecipeBuilder::new("fa_ib", &formats.ternary_imm8, 2)
.operands_in(vec![fpr, fpr])
.operands_out(vec![0])
.inst_predicate(InstructionPredicate::new_is_unsigned_int(
&*formats.insert_lane,
"lane",
&*formats.ternary_imm8,
"imm",
8,
0,
))
@@ -621,7 +621,7 @@ pub(crate) fn define<'shared>(
r#"
{{PUT_OP}}(bits, rex2(in_reg1, in_reg0), sink);
modrm_rr(in_reg1, in_reg0, sink);
let imm:i64 = lane.into();
let imm: i64 = imm.into();
sink.put1(imm as u8);
"#,
),
@@ -1040,12 +1040,12 @@ pub(crate) fn define<'shared>(
// XX /r ib with 8-bit unsigned immediate (e.g. for insertlane)
{
recipes.add_template_inferred(
EncodingRecipeBuilder::new("r_ib_unsigned_r", &formats.insert_lane, 2)
EncodingRecipeBuilder::new("r_ib_unsigned_r", &formats.ternary_imm8, 2)
.operands_in(vec![fpr, gpr])
.operands_out(vec![0])
.inst_predicate(InstructionPredicate::new_is_unsigned_int(
&*formats.insert_lane,
"lane",
&*formats.ternary_imm8,
"imm",
8,
0,
))
@@ -1053,7 +1053,7 @@ pub(crate) fn define<'shared>(
r#"
{{PUT_OP}}(bits, rex2(in_reg1, in_reg0), sink);
modrm_rr(in_reg1, in_reg0, sink);
let imm:i64 = lane.into();
let imm: i64 = imm.into();
sink.put1(imm as u8);
"#,
),

14
cranelift/codegen/meta/src/shared/formats.rs
View File

@@ -24,7 +24,6 @@ pub(crate) struct Formats {
pub(crate) func_addr: Rc<InstructionFormat>,
pub(crate) heap_addr: Rc<InstructionFormat>,
pub(crate) indirect_jump: Rc<InstructionFormat>,
pub(crate) insert_lane: Rc<InstructionFormat>,
pub(crate) int_compare: Rc<InstructionFormat>,
pub(crate) int_compare_imm: Rc<InstructionFormat>,
pub(crate) int_cond: Rc<InstructionFormat>,
@@ -45,6 +44,7 @@ pub(crate) struct Formats {
pub(crate) store_complex: Rc<InstructionFormat>,
pub(crate) table_addr: Rc<InstructionFormat>,
pub(crate) ternary: Rc<InstructionFormat>,
pub(crate) ternary_imm8: Rc<InstructionFormat>,
pub(crate) trap: Rc<InstructionFormat>,
pub(crate) unary: Rc<InstructionFormat>,
pub(crate) unary_bool: Rc<InstructionFormat>,
@@ -88,18 +88,18 @@ impl Formats {
.typevar_operand(1)
.build(),
ternary_imm8: Builder::new("TernaryImm8")
.value()
.imm(&imm.uimm8)
.value()
.build(),
// Catch-all for instructions with many outputs and inputs and no immediate
// operands.
multiary: Builder::new("MultiAry").varargs().build(),
nullary: Builder::new("NullAry").build(),
insert_lane: Builder::new("InsertLane")
.value()
.imm_with_name("lane", &imm.uimm8)
.value()
.build(),
extract_lane: Builder::new("ExtractLane")
.value()
.imm_with_name("lane", &imm.uimm8)

4
cranelift/codegen/meta/src/shared/instructions.rs
View File

@@ -559,9 +559,9 @@ fn define_simd_lane_access(
The lane index, ``Idx``, is an immediate value, not an SSA value. It
must indicate a valid lane index for the type of ``x``.
"#,
&formats.insert_lane,
&formats.ternary_imm8,
)
.operands_in(vec![x, Idx, y])
.operands_in(vec![x, y, Idx])
.operands_out(vec![a]),
);

10
cranelift/codegen/src/isa/x86/enc_tables.rs
View File

@@ -1251,10 +1251,10 @@ fn convert_insertlane(
let mut pos = FuncCursor::new(func).at_inst(inst);
pos.use_srcloc(inst);
if let ir::InstructionData::InsertLane {
if let ir::InstructionData::TernaryImm8 {
opcode: ir::Opcode::Insertlane,
args: [vector, replacement],
lane,
imm: lane,
} = pos.func.dfg[inst]
{
let value_type = pos.func.dfg.value_type(vector);
@@ -1269,7 +1269,7 @@ fn convert_insertlane(
pos.func
.dfg
.replace(inst)
.x86_insertps(vector, immediate, replacement)
.x86_insertps(vector, replacement, immediate)
}
F64X2 => {
let replacement_as_vector = pos.ins().raw_bitcast(F64X2, replacement); // only necessary due to SSA types
@@ -1297,7 +1297,7 @@ fn convert_insertlane(
pos.func
.dfg
.replace(inst)
.x86_pinsr(vector, lane, replacement);
.x86_pinsr(vector, replacement, lane);
}
}
}
@@ -1340,7 +1340,7 @@ fn expand_dword_to_xmm<'f>(
if arg_type == I64 {
let (arg_lo, arg_hi) = pos.ins().isplit(arg);
let arg = pos.ins().scalar_to_vector(I32X4, arg_lo);
let arg = pos.ins().insertlane(arg, 1, arg_hi);
let arg = pos.ins().insertlane(arg, arg_hi, 1);
let arg = pos.ins().raw_bitcast(I64X2, arg);
arg
} else {

8
cranelift/codegen/src/verifier/mod.rs
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@@ -758,7 +758,7 @@ impl<'a> Verifier<'a> {
| Binary { .. }
| BinaryImm { .. }
| Ternary { .. }
| InsertLane { .. }
| TernaryImm8 { .. }
| ExtractLane { .. }
| Shuffle { .. }
| IntCompare { .. }
@@ -1918,14 +1918,14 @@ impl<'a> Verifier<'a> {
arg,
..
}
| ir::InstructionData::InsertLane {
| ir::InstructionData::TernaryImm8 {
opcode: ir::instructions::Opcode::Insertlane,
lane,
imm: lane,
args: [arg, _],
..
} => {
// We must be specific about the opcodes above because other instructions are using
// the ExtractLane/InsertLane formats.
// the same formats.
let ty = self.func.dfg.value_type(arg);
if u16::from(lane) >= ty.lane_count() {
errors.fatal((

2
cranelift/codegen/src/write.rs
View File

@@ -518,7 +518,7 @@ pub fn write_operands(
}
}
NullAry { .. } => write!(w, " "),
InsertLane { lane, args, .. } => write!(w, " {}, {}, {}", args[0], lane, args[1]),
TernaryImm8 { imm, args, .. } => write!(w, " {}, {}, {}", args[0], args[1], imm),
ExtractLane { lane, arg, .. } => write!(w, " {}, {}", arg, lane),
Shuffle { mask, args, .. } => {
let data = dfg.immediates.get(mask).expect(