riscv64: Don't reuse registers when loading constants (#5376)

Rework the constant loading functions in the riscv64 backend to generate fresh temporaries instead of reusing the destination register.

cranelift/filetests/filetests/isa/riscv64/amodes.clif

@@ -93,12 +93,12 @@ block0(v0: i64, v1: i64, v2: i64):
 }
 
 ; block0:
-;   add a5,a0,a1
-;   add a5,a5,a2
-;   lui a4,1
-;   addi a4,a4,4
-;   add a7,a5,a4
-;   lw a0,0(a7)
+;   add a6,a0,a1
+;   add a6,a6,a2
+;   lui a5,1
+;   addi a5,a5,4
+;   add t3,a6,a5
+;   lw a0,0(t3)
 ;   ret
 
 function %f10() -> i32 {
@@ -151,8 +151,8 @@ block0(v0: i64):
 ; block0:
 ;   lui a1,244141
 ;   addi a1,a1,2560
-;   add a3,a0,a1
-;   lw a0,0(a3)
+;   add a4,a0,a1
+;   lw a0,0(a4)
 ;   ret
 
 function %f14(i32) -> i32 {
@@ -192,10 +192,10 @@ block0(v0: i64, v1: i64, v2: i64):
 }
 
 ; block0:
-;   lui a2,1048575
-;   addi a2,a2,4094
-;   uext.w a5,a2
-;   lh a0,0(a5)
+;   lui a3,1048575
+;   addi a3,a3,4094
+;   uext.w a6,a3
+;   lh a0,0(a6)
 ;   ret
 
 function %f19(i64, i64, i64) -> i32 {
@@ -207,10 +207,10 @@ block0(v0: i64, v1: i64, v2: i64):
 }
 
 ; block0:
-;   lui a2,1
-;   addi a2,a2,2
-;   uext.w a5,a2
-;   lh a0,0(a5)
+;   lui a3,1
+;   addi a3,a3,2
+;   uext.w a6,a3
+;   lh a0,0(a6)
 ;   ret
 
 function %f20(i64, i64, i64) -> i32 {
@@ -222,10 +222,10 @@ block0(v0: i64, v1: i64, v2: i64):
 }
 
 ; block0:
-;   lui a2,1048575
-;   addi a2,a2,4094
-;   sext.w a5,a2
-;   lh a0,0(a5)
+;   lui a3,1048575
+;   addi a3,a3,4094
+;   sext.w a6,a3
+;   lh a0,0(a6)
 ;   ret
 
 function %f21(i64, i64, i64) -> i32 {
@@ -237,10 +237,10 @@ block0(v0: i64, v1: i64, v2: i64):
 }
 
 ; block0:
-;   lui a2,1
-;   addi a2,a2,2
-;   sext.w a5,a2
-;   lh a0,0(a5)
+;   lui a3,1
+;   addi a3,a3,2
+;   sext.w a6,a3
+;   lh a0,0(a6)
 ;   ret
 
 function %i128(i64) -> i128 {

cranelift/filetests/filetests/isa/riscv64/atomic_store.clif

@@ -33,9 +33,9 @@ block0(v0: i64):
 }
 
 ; block0:
-;   lui t2,3
-;   addi t2,t2,57
-;   atomic_store.i64 t2,(a0)
+;   lui a1,3
+;   addi a1,a1,57
+;   atomic_store.i64 a1,(a0)
 ;   ret
 
 function %atomic_store_i32(i32, i64) {
@@ -69,8 +69,8 @@ block0(v0: i64):
 }
 
 ; block0:
-;   lui t2,3
-;   addi t2,t2,57
-;   atomic_store.i32 t2,(a0)
+;   lui a1,3
+;   addi a1,a1,57
+;   atomic_store.i32 a1,(a0)
 ;   ret
 

cranelift/filetests/filetests/isa/riscv64/condbr.clif

@@ -452,10 +452,10 @@ block1:
 }
 
 ; block0:
-;   lui t2,16
-;   addi t2,t2,4095
-;   and a2,a0,t2
-;   beq a2,zero,taken(label1),not_taken(label2)
+;   lui a1,16
+;   addi a1,a1,4095
+;   and a3,a0,a1
+;   beq a3,zero,taken(label1),not_taken(label2)
 ; block1:
 ;   j label3
 ; block2:
@@ -474,10 +474,10 @@ block1:
 }
 
 ; block0:
-;   lui t2,16
-;   addi t2,t2,4095
-;   and a2,a0,t2
-;   bne a2,zero,taken(label1),not_taken(label2)
+;   lui a1,16
+;   addi a1,a1,4095
+;   and a3,a0,a1
+;   bne a3,zero,taken(label1),not_taken(label2)
 ; block1:
 ;   j label3
 ; block2:

cranelift/filetests/filetests/isa/riscv64/constants.clif

@@ -39,8 +39,8 @@ block0:
 }
 
 ; block0:
-;   lui a0,16
-;   addi a0,a0,4095
+;   lui t1,16
+;   addi a0,t1,4095
 ;   ret
 
 function %f() -> i64 {

cranelift/filetests/filetests/isa/riscv64/heap-addr.clif

@@ -74,13 +74,13 @@ block0(v0: i64, v1: i32):
 }
 
 ; block0:
-;   uext.w a6,a1
-;   add a7,a0,a6
-;   addi a7,a7,16
-;   lui a4,16
-;   addi a4,a4,4072
-;   ugt t3,a6,a4##ty=i64
-;   li t4,0
-;   selectif_spectre_guard a0,t4,a7##test=t3
+;   uext.w a7,a1
+;   add t3,a0,a7
+;   addi t3,t3,16
+;   lui a5,16
+;   addi a5,a5,4072
+;   ugt t4,a7,a5##ty=i64
+;   li t0,0
+;   selectif_spectre_guard a0,t0,t3##test=t4
 ;   ret
 

cranelift/filetests/filetests/isa/riscv64/i128-bmask.clif

@@ -95,11 +95,11 @@ block0(v0: i16):
 }
 
 ; block0:
-;   lui t2,16
-;   addi t2,t2,4095
-;   and a2,a0,t2
-;   li a4,-1
-;   select_reg a1,zero,a4##condition=(zero eq a2)
+;   lui a1,16
+;   addi a1,a1,4095
+;   and a3,a0,a1
+;   li a5,-1
+;   select_reg a1,zero,a5##condition=(zero eq a3)
 ;   mv a0,a1
 ;   ret
 

cranelift/filetests/filetests/isa/riscv64/iconst-icmp-small.clif

@@ -11,12 +11,12 @@ block0:
 }
 
 ; block0:
-;   lui t0,14
-;   addi t0,t0,3532
-;   lui a0,14
-;   addi a0,a0,3532
-;   uext.h a3,t0
-;   uext.h a5,a0
-;   ne a0,a3,a5##ty=i16
+;   lui t1,14
+;   addi t1,t1,3532
+;   lui a2,14
+;   addi a2,a2,3532
+;   uext.h a5,t1
+;   uext.h a7,a2
+;   ne a0,a5,a7##ty=i16
 ;   ret