aarch64: Migrate iadd and isub to ISLE
This commit is the first "meaty" instruction added to ISLE for the AArch64 backend. I chose to pick the first two in the current lowering's `match` statement, `isub` and `iadd`. These two turned out to be particularly interesting for a few reasons: * Both had clearly migratable-to-ISLE behavior along the lines of special-casing per type. For example 128-bit and vector arithmetic were both easily translateable. * The `iadd` instruction has special cases for fusing with a multiplication to generate `madd` which is expressed pretty easily in ISLE. * Otherwise both instructions had a number of forms where they attempted to interpret the RHS as various forms of constants, extends, or shifts. There's a bit of a design space of how best to represent this in ISLE and what I settled on was to have a special case for each form of instruction, and the special cases are somewhat duplicated between `iadd` and `isub`. There's custom "extractors" for the special cases and instructions that support these special cases will have an `rule`-per-case. Overall I think the ISLE transitioned pretty well. I don't think that the aarch64 backend is going to follow the x64 backend super closely, though. For example the x64 backend is having a helper-per-instruction at the moment but with AArch64 it seems to make more sense to only have a helper-per-enum-variant-of-`MInst`. This is because the same instruction (e.g. `ALUOp::Sub32`) can be expressed with multiple different forms depending on the payload. It's worth noting that the ISLE looks like it's a good deal larger than the code actually being removed from lowering as part of this commit. I think this is deceptive though because a lot of the logic in `put_input_in_rse_imm12_maybe_negated` and `alu_inst_imm12` is being inlined into the ISLE definitions for each instruction instead of having it all packed into the helper functions. Some of the "boilerplate" here is the addition of various ISLE utilities as well.
This commit is contained in:
Alex Crichton
@@ -42,7 +42,7 @@ pub(crate) fn lower_insn_to_regs<C: LowerCtx<I = Inst>>(
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return Ok(());
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}
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let implemented_in_isle = || {
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let implemented_in_isle = |ctx: &mut C| {
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unreachable!(
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"implemented in ISLE: inst = `{}`, type = `{:?}`",
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ctx.dfg().display_inst(insn),
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@@ -51,7 +51,7 @@ pub(crate) fn lower_insn_to_regs<C: LowerCtx<I = Inst>>(
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};
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match op {
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Opcode::Iconst | Opcode::Bconst | Opcode::Null => implemented_in_isle(),
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Opcode::Iconst | Opcode::Bconst | Opcode::Null => implemented_in_isle(ctx),
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Opcode::F32const => {
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let value = f32::from_bits(ctx.get_constant(insn).unwrap() as u32);
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@@ -63,143 +63,8 @@ pub(crate) fn lower_insn_to_regs<C: LowerCtx<I = Inst>>(
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let rd = get_output_reg(ctx, outputs[0]).only_reg().unwrap();
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lower_constant_f64(ctx, rd, value);
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}
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Opcode::Iadd => {
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match ty.unwrap() {
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ty if ty.is_vector() => {
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let rd = get_output_reg(ctx, outputs[0]).only_reg().unwrap();
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let rm = put_input_in_reg(ctx, inputs[1], NarrowValueMode::None);
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let rn = put_input_in_reg(ctx, inputs[0], NarrowValueMode::None);
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ctx.emit(Inst::VecRRR {
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rd,
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rn,
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rm,
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alu_op: VecALUOp::Add,
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size: VectorSize::from_ty(ty),
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});
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}
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I128 => {
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let lhs = put_input_in_regs(ctx, inputs[0]);
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let rhs = put_input_in_regs(ctx, inputs[1]);
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let dst = get_output_reg(ctx, outputs[0]);
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assert_eq!(lhs.len(), 2);
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assert_eq!(rhs.len(), 2);
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assert_eq!(dst.len(), 2);
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// adds x0, x0, x2
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// adc x1, x1, x3
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ctx.emit(Inst::AluRRR {
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alu_op: ALUOp::AddS64,
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rd: dst.regs()[0],
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rn: lhs.regs()[0],
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rm: rhs.regs()[0],
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});
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ctx.emit(Inst::AluRRR {
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alu_op: ALUOp::Adc64,
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rd: dst.regs()[1],
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rn: lhs.regs()[1],
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rm: rhs.regs()[1],
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});
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}
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ty => {
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let rd = get_output_reg(ctx, outputs[0]).only_reg().unwrap();
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let mul_insn = if let Some(mul_insn) =
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maybe_input_insn(ctx, inputs[1], Opcode::Imul)
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{
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Some((mul_insn, 0))
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} else if let Some(mul_insn) = maybe_input_insn(ctx, inputs[0], Opcode::Imul) {
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Some((mul_insn, 1))
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} else {
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None
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};
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// If possible combine mul + add into madd.
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if let Some((insn, addend_idx)) = mul_insn {
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let alu_op = choose_32_64(ty, ALUOp3::MAdd32, ALUOp3::MAdd64);
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let rn_input = InsnInput { insn, input: 0 };
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let rm_input = InsnInput { insn, input: 1 };
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let rn = put_input_in_reg(ctx, rn_input, NarrowValueMode::None);
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let rm = put_input_in_reg(ctx, rm_input, NarrowValueMode::None);
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let ra = put_input_in_reg(ctx, inputs[addend_idx], NarrowValueMode::None);
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ctx.emit(Inst::AluRRRR {
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alu_op,
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rd,
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rn,
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rm,
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ra,
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});
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} else {
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let rn = put_input_in_reg(ctx, inputs[0], NarrowValueMode::None);
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let (rm, negated) = put_input_in_rse_imm12_maybe_negated(
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ctx,
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inputs[1],
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ty_bits(ty),
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NarrowValueMode::None,
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);
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let alu_op = if !negated {
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choose_32_64(ty, ALUOp::Add32, ALUOp::Add64)
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} else {
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choose_32_64(ty, ALUOp::Sub32, ALUOp::Sub64)
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};
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ctx.emit(alu_inst_imm12(alu_op, rd, rn, rm));
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}
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}
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}
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}
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Opcode::Isub => {
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let ty = ty.unwrap();
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if ty == I128 {
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let lhs = put_input_in_regs(ctx, inputs[0]);
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let rhs = put_input_in_regs(ctx, inputs[1]);
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let dst = get_output_reg(ctx, outputs[0]);
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assert_eq!(lhs.len(), 2);
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assert_eq!(rhs.len(), 2);
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assert_eq!(dst.len(), 2);
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// subs x0, x0, x2
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// sbc x1, x1, x3
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ctx.emit(Inst::AluRRR {
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alu_op: ALUOp::SubS64,
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rd: dst.regs()[0],
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rn: lhs.regs()[0],
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rm: rhs.regs()[0],
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});
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ctx.emit(Inst::AluRRR {
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alu_op: ALUOp::Sbc64,
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rd: dst.regs()[1],
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rn: lhs.regs()[1],
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rm: rhs.regs()[1],
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});
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} else {
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let rd = get_output_reg(ctx, outputs[0]).only_reg().unwrap();
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let rn = put_input_in_reg(ctx, inputs[0], NarrowValueMode::None);
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if !ty.is_vector() {
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let (rm, negated) = put_input_in_rse_imm12_maybe_negated(
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ctx,
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inputs[1],
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ty_bits(ty),
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NarrowValueMode::None,
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);
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let alu_op = if !negated {
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choose_32_64(ty, ALUOp::Sub32, ALUOp::Sub64)
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} else {
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choose_32_64(ty, ALUOp::Add32, ALUOp::Add64)
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};
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ctx.emit(alu_inst_imm12(alu_op, rd, rn, rm));
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} else {
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let rm = put_input_in_reg(ctx, inputs[1], NarrowValueMode::None);
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ctx.emit(Inst::VecRRR {
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rd,
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rn,
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rm,
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alu_op: VecALUOp::Sub,
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size: VectorSize::from_ty(ty),
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});
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}
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}
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}
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Opcode::Iadd => implemented_in_isle(ctx),
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Opcode::Isub => implemented_in_isle(ctx),
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Opcode::UaddSat | Opcode::SaddSat | Opcode::UsubSat | Opcode::SsubSat => {
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let ty = ty.unwrap();
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