aarch64: Migrate iadd and isub to ISLE
This commit is the first "meaty" instruction added to ISLE for the AArch64 backend. I chose to pick the first two in the current lowering's `match` statement, `isub` and `iadd`. These two turned out to be particularly interesting for a few reasons: * Both had clearly migratable-to-ISLE behavior along the lines of special-casing per type. For example 128-bit and vector arithmetic were both easily translateable. * The `iadd` instruction has special cases for fusing with a multiplication to generate `madd` which is expressed pretty easily in ISLE. * Otherwise both instructions had a number of forms where they attempted to interpret the RHS as various forms of constants, extends, or shifts. There's a bit of a design space of how best to represent this in ISLE and what I settled on was to have a special case for each form of instruction, and the special cases are somewhat duplicated between `iadd` and `isub`. There's custom "extractors" for the special cases and instructions that support these special cases will have an `rule`-per-case. Overall I think the ISLE transitioned pretty well. I don't think that the aarch64 backend is going to follow the x64 backend super closely, though. For example the x64 backend is having a helper-per-instruction at the moment but with AArch64 it seems to make more sense to only have a helper-per-enum-variant-of-`MInst`. This is because the same instruction (e.g. `ALUOp::Sub32`) can be expressed with multiple different forms depending on the payload. It's worth noting that the ISLE looks like it's a good deal larger than the code actually being removed from lowering as part of this commit. I think this is deceptive though because a lot of the logic in `put_input_in_rse_imm12_maybe_negated` and `alu_inst_imm12` is being inlined into the ISLE definitions for each instruction instead of having it all packed into the helper functions. Some of the "boilerplate" here is the addition of various ISLE utilities as well.
This commit is contained in:
Alex Crichton
@@ -21,3 +21,128 @@
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(rule (lower (has_type ty (null)))
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(value_reg (imm ty 0)))
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;;;; Rules for `iadd` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; `i64` and smaller
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;; base case, simply adding things in registers
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(rule (lower (has_type (fits_in_64 ty) (iadd x y)))
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(value_reg (alu_rrr (iadd_op ty) (put_in_reg x) (put_in_reg y))))
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;; special case for when one operand is an immediate that fits in 12 bits
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(rule (lower (has_type (fits_in_64 ty) (iadd x (imm12_from_value y))))
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(value_reg (alu_rr_imm12 (iadd_op ty) (put_in_reg x) y)))
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;; same as the previous special case, except we can switch the addition to a
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;; subtraction if the negated immediate fits in 12 bits.
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(rule (lower (has_type (fits_in_64 ty) (iadd x (imm12_from_negated_value y))))
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(value_reg (alu_rr_imm12 (isub_op ty) (put_in_reg x) y)))
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;; special case for when we're adding an extended register where the extending
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;; operation can get folded into the add itself.
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(rule (lower (has_type (fits_in_64 ty) (iadd x (extended_value_from_value y))))
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(value_reg (alu_rr_extend_reg (iadd_op ty) (put_in_reg x) y)))
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;; special case for when we're adding the shift of a different
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;; register by a constant amount and the shift can get folded into the add.
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(rule (lower (has_type (fits_in_64 ty)
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(iadd x (def_inst (ishl y (def_inst (iconst (lshl_from_imm64 <ty amt))))))))
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(value_reg (alu_rrr_shift (iadd_op ty) (put_in_reg x) (put_in_reg y) amt)))
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;; Fold an `iadd` and `imul` combination into a `madd` instruction
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(rule (lower (has_type (fits_in_64 ty) (iadd x (def_inst (imul y z)))))
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(value_reg (alu_rrrr (madd_op ty) (put_in_reg y) (put_in_reg z) (put_in_reg x))))
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(rule (lower (has_type (fits_in_64 ty) (iadd (def_inst (imul x y)) z)))
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(value_reg (alu_rrrr (madd_op ty) (put_in_reg x) (put_in_reg y) (put_in_reg z))))
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;; helper to use either a 32 or 64-bit add depending on the input type
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(decl iadd_op (Type) ALUOp)
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(rule (iadd_op (fits_in_32 _ty)) (ALUOp.Add32))
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(rule (iadd_op _ty) (ALUOp.Add64))
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;; helper to use either a 32 or 64-bit sub depending on the input type
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(decl isub_op (Type) ALUOp)
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(rule (isub_op (fits_in_32 _ty)) (ALUOp.Sub32))
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(rule (isub_op _ty) (ALUOp.Sub64))
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;; helper to use either a 32 or 64-bit madd depending on the input type
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(decl madd_op (Type) ALUOp3)
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(rule (madd_op (fits_in_32 _ty)) (ALUOp3.MAdd32))
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(rule (madd_op _ty) (ALUOp3.MAdd64))
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;; vectors
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(rule (lower (has_type ty @ (multi_lane _ _) (iadd x y)))
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(value_reg (vec_rrr (VecALUOp.Add) (put_in_reg x) (put_in_reg y) (vector_size ty))))
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;; `i128`
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(rule (lower (has_type $I128 (iadd x y)))
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(let (
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;; Get the high/low registers for `x`.
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(x_regs ValueRegs (put_in_regs x))
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(x_lo Reg (value_regs_get x_regs 0))
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(x_hi Reg (value_regs_get x_regs 1))
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;; Get the high/low registers for `y`.
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(y_regs ValueRegs (put_in_regs y))
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(y_lo Reg (value_regs_get y_regs 0))
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(y_hi Reg (value_regs_get y_regs 1))
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)
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;; the actual addition is `adds` followed by `adc` which comprises the
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;; low/high bits of the result
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(value_regs
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(alu_rrr (ALUOp.AddS64) x_lo y_lo)
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(alu_rrr (ALUOp.Adc64) x_hi y_hi))))
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;;;; Rules for `isub` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; `i64` and smaller
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;; base case, simply subtracting things in registers
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(rule (lower (has_type (fits_in_64 ty) (isub x y)))
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(value_reg (alu_rrr (isub_op ty) (put_in_reg x) (put_in_reg y))))
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;; special case for when one operand is an immediate that fits in 12 bits
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(rule (lower (has_type (fits_in_64 ty) (isub x (imm12_from_value y))))
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(value_reg (alu_rr_imm12 (isub_op ty) (put_in_reg x) y)))
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;; same as the previous special case, except we can switch the subtraction to an
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;; addition if the negated immediate fits in 12 bits.
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(rule (lower (has_type (fits_in_64 ty) (isub x (imm12_from_negated_value y))))
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(value_reg (alu_rr_imm12 (iadd_op ty) (put_in_reg x) y)))
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;; special cases for when we're subtracting an extended register where the
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;; extending operation can get folded into the sub itself.
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(rule (lower (has_type (fits_in_64 ty) (isub x (extended_value_from_value y))))
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(value_reg (alu_rr_extend_reg (isub_op ty) (put_in_reg x) y)))
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;; finally a special case for when we're subtracting the shift of a different
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;; register by a constant amount and the shift can get folded into the sub.
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(rule (lower (has_type (fits_in_64 ty)
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(isub x (def_inst (ishl y (def_inst (iconst (lshl_from_imm64 <ty amt))))))))
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(value_reg (alu_rrr_shift (isub_op ty) (put_in_reg x) (put_in_reg y) amt)))
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;; vectors
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(rule (lower (has_type ty @ (multi_lane _ _) (isub x y)))
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(value_reg (vec_rrr (VecALUOp.Sub) (put_in_reg x) (put_in_reg y) (vector_size ty))))
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;; `i128`
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(rule (lower (has_type $I128 (isub x y)))
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(let (
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;; Get the high/low registers for `x`.
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(x_regs ValueRegs (put_in_regs x))
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(x_lo Reg (value_regs_get x_regs 0))
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(x_hi Reg (value_regs_get x_regs 1))
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;; Get the high/low registers for `y`.
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(y_regs ValueRegs (put_in_regs y))
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(y_lo Reg (value_regs_get y_regs 0))
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(y_hi Reg (value_regs_get y_regs 1))
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)
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;; the actual subtraction is `subs` followed by `sbc` which comprises
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;; the low/high bits of the result
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(value_regs
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(alu_rrr (ALUOp.SubS64) x_lo y_lo)
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(alu_rrr (ALUOp.Sbc64) x_hi y_hi))))
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