aarch64: Migrate iadd and isub to ISLE
This commit is the first "meaty" instruction added to ISLE for the AArch64 backend. I chose to pick the first two in the current lowering's `match` statement, `isub` and `iadd`. These two turned out to be particularly interesting for a few reasons: * Both had clearly migratable-to-ISLE behavior along the lines of special-casing per type. For example 128-bit and vector arithmetic were both easily translateable. * The `iadd` instruction has special cases for fusing with a multiplication to generate `madd` which is expressed pretty easily in ISLE. * Otherwise both instructions had a number of forms where they attempted to interpret the RHS as various forms of constants, extends, or shifts. There's a bit of a design space of how best to represent this in ISLE and what I settled on was to have a special case for each form of instruction, and the special cases are somewhat duplicated between `iadd` and `isub`. There's custom "extractors" for the special cases and instructions that support these special cases will have an `rule`-per-case. Overall I think the ISLE transitioned pretty well. I don't think that the aarch64 backend is going to follow the x64 backend super closely, though. For example the x64 backend is having a helper-per-instruction at the moment but with AArch64 it seems to make more sense to only have a helper-per-enum-variant-of-`MInst`. This is because the same instruction (e.g. `ALUOp::Sub32`) can be expressed with multiple different forms depending on the payload. It's worth noting that the ISLE looks like it's a good deal larger than the code actually being removed from lowering as part of this commit. I think this is deceptive though because a lot of the logic in `put_input_in_rse_imm12_maybe_negated` and `alu_inst_imm12` is being inlined into the ISLE definitions for each instruction instead of having it all packed into the helper functions. Some of the "boilerplate" here is the addition of various ISLE utilities as well.
This commit is contained in:
Alex Crichton
@@ -947,6 +947,13 @@
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(Size64x2)
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))
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;; Helper for calculating the `VectorSize` corresponding to a type
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(decl vector_size (Type) VectorSize)
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(rule (vector_size (multi_lane 8 16)) (VectorSize.Size8x16))
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(rule (vector_size (multi_lane 16 8)) (VectorSize.Size16x8))
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(rule (vector_size (multi_lane 32 4)) (VectorSize.Size32x4))
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(rule (vector_size (multi_lane 64 2)) (VectorSize.Size64x2))
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;; A floating-point unit (FPU) operation with one arg.
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(type FPUOp1
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(enum
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@@ -1294,9 +1301,41 @@
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(decl imm_logic_from_u64 (ImmLogic) u64)
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(extern extractor imm_logic_from_u64 imm_logic_from_u64)
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(decl imm12_from_u64 (Imm12) u64)
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(extern extractor imm12_from_u64 imm12_from_u64)
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(decl imm12_from_negated_u64 (Imm12) u64)
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(extern extractor imm12_from_negated_u64 imm12_from_negated_u64)
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(decl lshl_from_imm64 (Type ShiftOpAndAmt) Imm64)
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(extern extractor lshl_from_imm64 lshl_from_imm64 (in out))
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(decl integral_ty (Type) Type)
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(extern extractor integral_ty integral_ty)
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;; Helper to go directly from a `Value`, when it's an `iconst`, to an `Imm12`.
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(decl imm12_from_value (Imm12) Value)
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(extractor
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(imm12_from_value n)
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(def_inst (iconst (u64_from_imm64 (imm12_from_u64 n)))))
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;; Same as `imm12_from_value`, but tries negating the constant value.
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(decl imm12_from_negated_value (Imm12) Value)
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(extractor
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(imm12_from_negated_value n)
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(def_inst (iconst (u64_from_imm64 (imm12_from_negated_u64 n)))))
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;; Helper type to represent a value and an extend operation fused together.
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(type ExtendedValue extern (enum))
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(decl extended_value_from_value (ExtendedValue) Value)
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(extern extractor extended_value_from_value extended_value_from_value)
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;; Constructors used to poke at the fields of an `ExtendedValue`.
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(decl put_extended_in_reg (ExtendedValue) Reg)
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(extern constructor put_extended_in_reg put_extended_in_reg)
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(decl get_extended_op (ExtendedValue) ExtendOp)
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(extern constructor get_extended_op get_extended_op)
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;; Instruction creation helpers ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; Emit an instruction.
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@@ -1331,9 +1370,55 @@
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(_ Unit (emit (MInst.AluRRImmLogic op dst src imm))))
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(writable_reg_to_reg dst)))
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;; Helper for emitting `orr64` instructions.
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(decl orr64 (Reg ImmLogic) Reg)
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(rule (orr64 src imm) (alu_rr_imm_logic (ALUOp.Orr64) src imm))
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;; Helper for emitting `MInst.AluRRR` instructions.
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(decl alu_rrr (ALUOp Reg Reg) Reg)
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(rule (alu_rrr op src1 src2)
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(let ((dst WritableReg (temp_writable_reg $I64))
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(_ Unit (emit (MInst.AluRRR op dst src1 src2))))
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(writable_reg_to_reg dst)))
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;; Helper for emitting `MInst.VecRRR` instructions.
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(decl vec_rrr (VecALUOp Reg Reg VectorSize) Reg)
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(rule (vec_rrr op src1 src2 size)
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(let ((dst WritableReg (temp_writable_reg $I8X16))
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(_ Unit (emit (MInst.VecRRR op dst src1 src2 size))))
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(writable_reg_to_reg dst)))
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;; Helper for emitting `MInst.AluRRImm12` instructions.
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(decl alu_rr_imm12 (ALUOp Reg Imm12) Reg)
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(rule (alu_rr_imm12 op src imm)
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(let ((dst WritableReg (temp_writable_reg $I64))
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(_ Unit (emit (MInst.AluRRImm12 op dst src imm))))
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(writable_reg_to_reg dst)))
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;; Helper for emitting `MInst.AluRRRShift` instructions.
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(decl alu_rrr_shift (ALUOp Reg Reg ShiftOpAndAmt) Reg)
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(rule (alu_rrr_shift op src1 src2 shift)
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(let ((dst WritableReg (temp_writable_reg $I64))
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(_ Unit (emit (MInst.AluRRRShift op dst src1 src2 shift))))
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(writable_reg_to_reg dst)))
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;; Helper for emitting `MInst.AluRRRExtend` instructions.
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(decl alu_rrr_extend (ALUOp Reg Reg ExtendOp) Reg)
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(rule (alu_rrr_extend op src1 src2 extend)
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(let ((dst WritableReg (temp_writable_reg $I64))
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(_ Unit (emit (MInst.AluRRRExtend op dst src1 src2 extend))))
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(writable_reg_to_reg dst)))
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;; Same as `alu_rrr_extend`, but takes an `ExtendedValue` packed "pair" instead
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;; of a `Reg` and an `ExtendOp`.
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(decl alu_rr_extend_reg (ALUOp Reg ExtendedValue) Reg)
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(rule (alu_rr_extend_reg op src1 extended_reg)
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(let ((src2 Reg (put_extended_in_reg extended_reg))
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(extend ExtendOp (get_extended_op extended_reg)))
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(alu_rrr_extend op src1 src2 extend)))
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;; Helper for emitting `MInst.AluRRRR` instructions.
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(decl alu_rrrr (ALUOp3 Reg Reg Reg) Reg)
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(rule (alu_rrrr op src1 src2 src3)
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(let ((dst WritableReg (temp_writable_reg $I64))
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(_ Unit (emit (MInst.AluRRRR op dst src1 src2 src3))))
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(writable_reg_to_reg dst)))
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;; Immediate value helpers ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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@@ -1349,7 +1434,7 @@
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;; Weird logical-instruction immediate in ORI using zero register
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(rule (imm (integral_ty _ty) (imm_logic_from_u64 n))
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(orr64 (zero_reg) n))
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(alu_rr_imm_logic (ALUOp.Orr64) (zero_reg) n))
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(decl load_constant64_full (u64) Reg)
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(extern constructor load_constant64_full load_constant64_full)
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