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[AArch64] Merge 32- and 64-bit FPUOp2 (#4029)

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And remove the unused saturating add/sub opcodes.

Copyright (c) 2022, Arm Limited.
This commit is contained in:
Sam Parker
2022-04-14 21:07:00 +01:00
committed by GitHub
parent e142f587a7
commit 7c0ea28fc8
7 changed files with 236 additions and 301 deletions
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31
cranelift/codegen/src/isa/aarch64/inst/emit.rs
View File

@@ -1686,28 +1686,25 @@ impl MachInstEmit for Inst {
};
sink.put4(enc_fpurr(top22, rd, rn));
}
&Inst::FpuRRR { fpu_op, rd, rn, rm } => {
&Inst::FpuRRR {
fpu_op,
size,
rd,
rn,
rm,
} => {
let rd = allocs.next_writable(rd);
let rn = allocs.next(rn);
let rm = allocs.next(rm);
let top22 = match fpu_op {
FPUOp2::Add32 => 0b000_11110_00_1_00000_001010,
FPUOp2::Add64 => 0b000_11110_01_1_00000_001010,
FPUOp2::Sub32 => 0b000_11110_00_1_00000_001110,
FPUOp2::Sub64 => 0b000_11110_01_1_00000_001110,
FPUOp2::Mul32 => 0b000_11110_00_1_00000_000010,
FPUOp2::Mul64 => 0b000_11110_01_1_00000_000010,
FPUOp2::Div32 => 0b000_11110_00_1_00000_000110,
FPUOp2::Div64 => 0b000_11110_01_1_00000_000110,
FPUOp2::Max32 => 0b000_11110_00_1_00000_010010,
FPUOp2::Max64 => 0b000_11110_01_1_00000_010010,
FPUOp2::Min32 => 0b000_11110_00_1_00000_010110,
FPUOp2::Min64 => 0b000_11110_01_1_00000_010110,
FPUOp2::Sqadd64 => 0b010_11110_11_1_00000_000011,
FPUOp2::Uqadd64 => 0b011_11110_11_1_00000_000011,
FPUOp2::Sqsub64 => 0b010_11110_11_1_00000_001011,
FPUOp2::Uqsub64 => 0b011_11110_11_1_00000_001011,
FPUOp2::Add => 0b000_11110_00_1_00000_001010,
FPUOp2::Sub => 0b000_11110_00_1_00000_001110,
FPUOp2::Mul => 0b000_11110_00_1_00000_000010,
FPUOp2::Div => 0b000_11110_00_1_00000_000110,
FPUOp2::Max => 0b000_11110_00_1_00000_010010,
FPUOp2::Min => 0b000_11110_00_1_00000_010110,
};
let top22 = top22 | size.ftype() << 12;
sink.put4(enc_fpurrr(top22, rd, rn, rm));
}
&Inst::FpuRRI { fpu_op, rd, rn } => {

80
cranelift/codegen/src/isa/aarch64/inst/emit_tests.rs
View File

@@ -5428,7 +5428,8 @@ fn test_aarch64_binemit() {
insns.push((
Inst::FpuRRR {
fpu_op: FPUOp2::Add32,
fpu_op: FPUOp2::Add,
size: ScalarSize::Size32,
rd: writable_vreg(15),
rn: vreg(30),
rm: vreg(31),
@@ -5439,7 +5440,8 @@ fn test_aarch64_binemit() {
insns.push((
Inst::FpuRRR {
fpu_op: FPUOp2::Add64,
fpu_op: FPUOp2::Add,
size: ScalarSize::Size64,
rd: writable_vreg(15),
rn: vreg(30),
rm: vreg(31),
@@ -5450,7 +5452,8 @@ fn test_aarch64_binemit() {
insns.push((
Inst::FpuRRR {
fpu_op: FPUOp2::Sub32,
fpu_op: FPUOp2::Sub,
size: ScalarSize::Size32,
rd: writable_vreg(15),
rn: vreg(30),
rm: vreg(31),
@@ -5461,7 +5464,8 @@ fn test_aarch64_binemit() {
insns.push((
Inst::FpuRRR {
fpu_op: FPUOp2::Sub64,
fpu_op: FPUOp2::Sub,
size: ScalarSize::Size64,
rd: writable_vreg(15),
rn: vreg(30),
rm: vreg(31),
@@ -5472,7 +5476,8 @@ fn test_aarch64_binemit() {
insns.push((
Inst::FpuRRR {
fpu_op: FPUOp2::Mul32,
fpu_op: FPUOp2::Mul,
size: ScalarSize::Size32,
rd: writable_vreg(15),
rn: vreg(30),
rm: vreg(31),
@@ -5483,7 +5488,8 @@ fn test_aarch64_binemit() {
insns.push((
Inst::FpuRRR {
fpu_op: FPUOp2::Mul64,
fpu_op: FPUOp2::Mul,
size: ScalarSize::Size64,
rd: writable_vreg(15),
rn: vreg(30),
rm: vreg(31),
@@ -5494,7 +5500,8 @@ fn test_aarch64_binemit() {
insns.push((
Inst::FpuRRR {
fpu_op: FPUOp2::Div32,
fpu_op: FPUOp2::Div,
size: ScalarSize::Size32,
rd: writable_vreg(15),
rn: vreg(30),
rm: vreg(31),
@@ -5505,7 +5512,8 @@ fn test_aarch64_binemit() {
insns.push((
Inst::FpuRRR {
fpu_op: FPUOp2::Div64,
fpu_op: FPUOp2::Div,
size: ScalarSize::Size64,
rd: writable_vreg(15),
rn: vreg(30),
rm: vreg(31),
@@ -5516,7 +5524,8 @@ fn test_aarch64_binemit() {
insns.push((
Inst::FpuRRR {
fpu_op: FPUOp2::Max32,
fpu_op: FPUOp2::Max,
size: ScalarSize::Size32,
rd: writable_vreg(15),
rn: vreg(30),
rm: vreg(31),
@@ -5527,7 +5536,8 @@ fn test_aarch64_binemit() {
insns.push((
Inst::FpuRRR {
fpu_op: FPUOp2::Max64,
fpu_op: FPUOp2::Max,
size: ScalarSize::Size64,
rd: writable_vreg(15),
rn: vreg(30),
rm: vreg(31),
@@ -5538,7 +5548,8 @@ fn test_aarch64_binemit() {
insns.push((
Inst::FpuRRR {
fpu_op: FPUOp2::Min32,
fpu_op: FPUOp2::Min,
size: ScalarSize::Size32,
rd: writable_vreg(15),
rn: vreg(30),
rm: vreg(31),
@@ -5549,7 +5560,8 @@ fn test_aarch64_binemit() {
insns.push((
Inst::FpuRRR {
fpu_op: FPUOp2::Min64,
fpu_op: FPUOp2::Min,
size: ScalarSize::Size64,
rd: writable_vreg(15),
rn: vreg(30),
rm: vreg(31),
@@ -5558,50 +5570,6 @@ fn test_aarch64_binemit() {
"fmin d15, d30, d31",
));
insns.push((
Inst::FpuRRR {
fpu_op: FPUOp2::Uqadd64,
rd: writable_vreg(21),
rn: vreg(22),
rm: vreg(23),
},
"D50EF77E",
"uqadd d21, d22, d23",
));
insns.push((
Inst::FpuRRR {
fpu_op: FPUOp2::Sqadd64,
rd: writable_vreg(21),
rn: vreg(22),
rm: vreg(23),
},
"D50EF75E",
"sqadd d21, d22, d23",
));
insns.push((
Inst::FpuRRR {
fpu_op: FPUOp2::Uqsub64,
rd: writable_vreg(21),
rn: vreg(22),
rm: vreg(23),
},
"D52EF77E",
"uqsub d21, d22, d23",
));
insns.push((
Inst::FpuRRR {
fpu_op: FPUOp2::Sqsub64,
rd: writable_vreg(21),
rn: vreg(22),
rm: vreg(23),
},
"D52EF75E",
"sqsub d21, d22, d23",
));
insns.push((
Inst::FpuRRRR {
fpu_op: FPUOp3::MAdd32,

32
cranelift/codegen/src/isa/aarch64/inst/mod.rs
View File

@@ -1690,24 +1690,20 @@ impl Inst {
let rn = pretty_print_vreg_scalar(rn, sizesrc, allocs);
format!("{} {}, {}", op, rd, rn)
}
&Inst::FpuRRR { fpu_op, rd, rn, rm } => {
let (op, size) = match fpu_op {
FPUOp2::Add32 => ("fadd", ScalarSize::Size32),
FPUOp2::Add64 => ("fadd", ScalarSize::Size64),
FPUOp2::Sub32 => ("fsub", ScalarSize::Size32),
FPUOp2::Sub64 => ("fsub", ScalarSize::Size64),
FPUOp2::Mul32 => ("fmul", ScalarSize::Size32),
FPUOp2::Mul64 => ("fmul", ScalarSize::Size64),
FPUOp2::Div32 => ("fdiv", ScalarSize::Size32),
FPUOp2::Div64 => ("fdiv", ScalarSize::Size64),
FPUOp2::Max32 => ("fmax", ScalarSize::Size32),
FPUOp2::Max64 => ("fmax", ScalarSize::Size64),
FPUOp2::Min32 => ("fmin", ScalarSize::Size32),
FPUOp2::Min64 => ("fmin", ScalarSize::Size64),
FPUOp2::Sqadd64 => ("sqadd", ScalarSize::Size64),
FPUOp2::Uqadd64 => ("uqadd", ScalarSize::Size64),
FPUOp2::Sqsub64 => ("sqsub", ScalarSize::Size64),
FPUOp2::Uqsub64 => ("uqsub", ScalarSize::Size64),
&Inst::FpuRRR {
fpu_op,
size,
rd,
rn,
rm,
} => {
let op = match fpu_op {
FPUOp2::Add => "fadd",
FPUOp2::Sub => "fsub",
FPUOp2::Mul => "fmul",
FPUOp2::Div => "fdiv",
FPUOp2::Max => "fmax",
FPUOp2::Min => "fmin",
};
let rd = pretty_print_vreg_scalar(rd.to_reg(), size, allocs);
let rn = pretty_print_vreg_scalar(rn, size, allocs);