Cranelift: implement heap_{load,store} instruction legalization (#5351)
* Cranelift: implement `heap_{load,store}` instruction legalization
This does not remove `heap_addr` yet, but it does factor out the common
bounds-check-and-compute-the-native-address functionality that is shared between
all of `heap_{addr,load,store}`.
Finally, this adds a missing optimization for when we can dedupe explicit bounds
checks for static memories and Spectre mitigations.
* Cranelift: Enable `heap_load_store_*` run tests on all targets
This commit is contained in:
@@ -1,14 +1,15 @@
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;; !!! GENERATED BY 'make-heap-load-store-tests.sh' DO NOT EDIT !!!
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test interpret
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;; test run
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;; target x86_64
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;; target s390x
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;; target aarch64
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;; target riscv64
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test run
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set enable_heap_access_spectre_mitigation=false
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target x86_64
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target s390x
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target aarch64
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target riscv64
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function %do_store(i64 vmctx, i32, i32) {
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gv0 = vmctx
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gv1 = load.i64 notrap aligned gv0+0
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@@ -1,14 +1,15 @@
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;; !!! GENERATED BY 'make-heap-load-store-tests.sh' DO NOT EDIT !!!
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test interpret
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;; test run
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;; target x86_64
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;; target s390x
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;; target aarch64
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;; target riscv64
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test run
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set enable_heap_access_spectre_mitigation=true
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target x86_64
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target s390x
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target aarch64
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target riscv64
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function %do_store(i64 vmctx, i32, i32) {
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gv0 = vmctx
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gv1 = load.i64 notrap aligned gv0+0
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@@ -1,14 +1,15 @@
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;; !!! GENERATED BY 'make-heap-load-store-tests.sh' DO NOT EDIT !!!
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test interpret
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;; test run
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;; target x86_64
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;; target s390x
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;; target aarch64
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;; target riscv64
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test run
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set enable_heap_access_spectre_mitigation=false
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target x86_64
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target s390x
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target aarch64
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target riscv64
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function %do_store(i64 vmctx, i32, i32) {
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gv0 = vmctx
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gv1 = load.i64 notrap aligned gv0+0
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@@ -1,14 +1,15 @@
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;; !!! GENERATED BY 'make-heap-load-store-tests.sh' DO NOT EDIT !!!
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test interpret
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;; test run
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;; target x86_64
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;; target s390x
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;; target aarch64
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;; target riscv64
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test run
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set enable_heap_access_spectre_mitigation=true
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target x86_64
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target s390x
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target aarch64
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target riscv64
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function %do_store(i64 vmctx, i32, i32) {
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gv0 = vmctx
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gv1 = load.i64 notrap aligned gv0+0
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@@ -1,14 +1,15 @@
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;; !!! GENERATED BY 'make-heap-load-store-tests.sh' DO NOT EDIT !!!
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test interpret
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;; test run
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;; target x86_64
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;; target s390x
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;; target aarch64
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;; target riscv64
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test run
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set enable_heap_access_spectre_mitigation=false
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target x86_64
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target s390x
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target aarch64
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target riscv64
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function %do_store(i64 vmctx, i64, i32) {
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gv0 = vmctx
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gv1 = load.i64 notrap aligned gv0+0
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@@ -1,14 +1,15 @@
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;; !!! GENERATED BY 'make-heap-load-store-tests.sh' DO NOT EDIT !!!
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test interpret
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;; test run
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;; target x86_64
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;; target s390x
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;; target aarch64
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;; target riscv64
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test run
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set enable_heap_access_spectre_mitigation=true
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target x86_64
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target s390x
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target aarch64
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target riscv64
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function %do_store(i64 vmctx, i64, i32) {
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gv0 = vmctx
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gv1 = load.i64 notrap aligned gv0+0
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@@ -1,14 +1,15 @@
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;; !!! GENERATED BY 'make-heap-load-store-tests.sh' DO NOT EDIT !!!
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test interpret
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;; test run
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;; target x86_64
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;; target s390x
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;; target aarch64
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;; target riscv64
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test run
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set enable_heap_access_spectre_mitigation=false
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target x86_64
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target s390x
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target aarch64
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target riscv64
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function %do_store(i64 vmctx, i64, i32) {
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gv0 = vmctx
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gv1 = load.i64 notrap aligned gv0+0
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@@ -1,14 +1,15 @@
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;; !!! GENERATED BY 'make-heap-load-store-tests.sh' DO NOT EDIT !!!
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test interpret
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;; test run
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;; target x86_64
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;; target s390x
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;; target aarch64
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;; target riscv64
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test run
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set enable_heap_access_spectre_mitigation=true
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target x86_64
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target s390x
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target aarch64
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target riscv64
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function %do_store(i64 vmctx, i64, i32) {
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gv0 = vmctx
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gv1 = load.i64 notrap aligned gv0+0
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@@ -1,14 +1,15 @@
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;; !!! GENERATED BY 'make-heap-load-store-tests.sh' DO NOT EDIT !!!
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test interpret
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;; test run
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;; target x86_64
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;; target s390x
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;; target aarch64
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;; target riscv64
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test run
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set enable_heap_access_spectre_mitigation=false
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target x86_64
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target s390x
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target aarch64
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target riscv64
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function %do_store(i64 vmctx, i32, i32) {
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gv0 = vmctx
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gv1 = load.i64 notrap aligned gv0+0
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@@ -1,14 +1,15 @@
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;; !!! GENERATED BY 'make-heap-load-store-tests.sh' DO NOT EDIT !!!
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test interpret
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;; test run
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;; target x86_64
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;; target s390x
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;; target aarch64
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;; target riscv64
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test run
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set enable_heap_access_spectre_mitigation=true
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target x86_64
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target s390x
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target aarch64
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target riscv64
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function %do_store(i64 vmctx, i32, i32) {
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gv0 = vmctx
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gv1 = load.i64 notrap aligned gv0+0
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@@ -1,14 +1,15 @@
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;; !!! GENERATED BY 'make-heap-load-store-tests.sh' DO NOT EDIT !!!
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test interpret
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;; test run
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;; target x86_64
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;; target s390x
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;; target aarch64
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;; target riscv64
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test run
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set enable_heap_access_spectre_mitigation=false
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target x86_64
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target s390x
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target aarch64
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target riscv64
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function %do_store(i64 vmctx, i32, i32) {
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gv0 = vmctx
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gv1 = load.i64 notrap aligned gv0+0
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@@ -1,14 +1,15 @@
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;; !!! GENERATED BY 'make-heap-load-store-tests.sh' DO NOT EDIT !!!
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test interpret
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;; test run
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;; target x86_64
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;; target s390x
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;; target aarch64
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;; target riscv64
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test run
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set enable_heap_access_spectre_mitigation=true
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target x86_64
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target s390x
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target aarch64
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target riscv64
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function %do_store(i64 vmctx, i32, i32) {
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gv0 = vmctx
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gv1 = load.i64 notrap aligned gv0+0
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@@ -1,14 +1,15 @@
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;; !!! GENERATED BY 'make-heap-load-store-tests.sh' DO NOT EDIT !!!
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test interpret
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;; test run
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;; target x86_64
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;; target s390x
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;; target aarch64
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;; target riscv64
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test run
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set enable_heap_access_spectre_mitigation=false
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target x86_64
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target s390x
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target aarch64
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target riscv64
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function %do_store(i64 vmctx, i64, i32) {
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gv0 = vmctx
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gv1 = load.i64 notrap aligned gv0+0
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@@ -1,14 +1,15 @@
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;; !!! GENERATED BY 'make-heap-load-store-tests.sh' DO NOT EDIT !!!
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test interpret
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;; test run
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;; target x86_64
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;; target s390x
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;; target aarch64
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;; target riscv64
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test run
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set enable_heap_access_spectre_mitigation=true
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target x86_64
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target s390x
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target aarch64
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target riscv64
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function %do_store(i64 vmctx, i64, i32) {
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gv0 = vmctx
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gv1 = load.i64 notrap aligned gv0+0
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@@ -1,14 +1,15 @@
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;; !!! GENERATED BY 'make-heap-load-store-tests.sh' DO NOT EDIT !!!
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test interpret
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;; test run
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;; target x86_64
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;; target s390x
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;; target aarch64
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;; target riscv64
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test run
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set enable_heap_access_spectre_mitigation=false
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target x86_64
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target s390x
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target aarch64
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target riscv64
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function %do_store(i64 vmctx, i64, i32) {
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gv0 = vmctx
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gv1 = load.i64 notrap aligned gv0+0
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@@ -1,14 +1,15 @@
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;; !!! GENERATED BY 'make-heap-load-store-tests.sh' DO NOT EDIT !!!
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test interpret
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;; test run
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;; target x86_64
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;; target s390x
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;; target aarch64
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;; target riscv64
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test run
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set enable_heap_access_spectre_mitigation=true
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target x86_64
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target s390x
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target aarch64
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target riscv64
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function %do_store(i64 vmctx, i64, i32) {
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gv0 = vmctx
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gv1 = load.i64 notrap aligned gv0+0
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@@ -39,14 +39,15 @@ function generate_one_test() {
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;; !!! GENERATED BY 'make-heap-load-store-tests.sh' DO NOT EDIT !!!
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test interpret
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;; test run
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;; target x86_64
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;; target s390x
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;; target aarch64
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;; target riscv64
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test run
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set enable_heap_access_spectre_mitigation=${enable_spectre}
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target x86_64
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target s390x
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target aarch64
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target riscv64
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function %do_store(i64 vmctx, ${index_type}, i32) {
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gv0 = vmctx
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gv1 = load.i64 notrap aligned gv0+0
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