Cranelift: implement heap_{load,store} instruction legalization (#5351)

* Cranelift: implement `heap_{load,store}` instruction legalization

This does not remove `heap_addr` yet, but it does factor out the common
bounds-check-and-compute-the-native-address functionality that is shared between
all of `heap_{addr,load,store}`.

Finally, this adds a missing optimization for when we can dedupe explicit bounds
checks for static memories and Spectre mitigations.

* Cranelift: Enable `heap_load_store_*` run tests on all targets
This commit is contained in:
Nick Fitzgerald
2022-11-30 11:12:49 -08:00
committed by GitHub
parent 830885383f
commit 79f7fa6079
27 changed files with 566 additions and 471 deletions

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@@ -1,14 +1,15 @@
;; !!! GENERATED BY 'make-heap-load-store-tests.sh' DO NOT EDIT !!!
test interpret
;; test run
;; target x86_64
;; target s390x
;; target aarch64
;; target riscv64
test run
set enable_heap_access_spectre_mitigation=false
target x86_64
target s390x
target aarch64
target riscv64
function %do_store(i64 vmctx, i32, i32) {
gv0 = vmctx
gv1 = load.i64 notrap aligned gv0+0

View File

@@ -1,14 +1,15 @@
;; !!! GENERATED BY 'make-heap-load-store-tests.sh' DO NOT EDIT !!!
test interpret
;; test run
;; target x86_64
;; target s390x
;; target aarch64
;; target riscv64
test run
set enable_heap_access_spectre_mitigation=true
target x86_64
target s390x
target aarch64
target riscv64
function %do_store(i64 vmctx, i32, i32) {
gv0 = vmctx
gv1 = load.i64 notrap aligned gv0+0

View File

@@ -1,14 +1,15 @@
;; !!! GENERATED BY 'make-heap-load-store-tests.sh' DO NOT EDIT !!!
test interpret
;; test run
;; target x86_64
;; target s390x
;; target aarch64
;; target riscv64
test run
set enable_heap_access_spectre_mitigation=false
target x86_64
target s390x
target aarch64
target riscv64
function %do_store(i64 vmctx, i32, i32) {
gv0 = vmctx
gv1 = load.i64 notrap aligned gv0+0

View File

@@ -1,14 +1,15 @@
;; !!! GENERATED BY 'make-heap-load-store-tests.sh' DO NOT EDIT !!!
test interpret
;; test run
;; target x86_64
;; target s390x
;; target aarch64
;; target riscv64
test run
set enable_heap_access_spectre_mitigation=true
target x86_64
target s390x
target aarch64
target riscv64
function %do_store(i64 vmctx, i32, i32) {
gv0 = vmctx
gv1 = load.i64 notrap aligned gv0+0

View File

@@ -1,14 +1,15 @@
;; !!! GENERATED BY 'make-heap-load-store-tests.sh' DO NOT EDIT !!!
test interpret
;; test run
;; target x86_64
;; target s390x
;; target aarch64
;; target riscv64
test run
set enable_heap_access_spectre_mitigation=false
target x86_64
target s390x
target aarch64
target riscv64
function %do_store(i64 vmctx, i64, i32) {
gv0 = vmctx
gv1 = load.i64 notrap aligned gv0+0

View File

@@ -1,14 +1,15 @@
;; !!! GENERATED BY 'make-heap-load-store-tests.sh' DO NOT EDIT !!!
test interpret
;; test run
;; target x86_64
;; target s390x
;; target aarch64
;; target riscv64
test run
set enable_heap_access_spectre_mitigation=true
target x86_64
target s390x
target aarch64
target riscv64
function %do_store(i64 vmctx, i64, i32) {
gv0 = vmctx
gv1 = load.i64 notrap aligned gv0+0

View File

@@ -1,14 +1,15 @@
;; !!! GENERATED BY 'make-heap-load-store-tests.sh' DO NOT EDIT !!!
test interpret
;; test run
;; target x86_64
;; target s390x
;; target aarch64
;; target riscv64
test run
set enable_heap_access_spectre_mitigation=false
target x86_64
target s390x
target aarch64
target riscv64
function %do_store(i64 vmctx, i64, i32) {
gv0 = vmctx
gv1 = load.i64 notrap aligned gv0+0

View File

@@ -1,14 +1,15 @@
;; !!! GENERATED BY 'make-heap-load-store-tests.sh' DO NOT EDIT !!!
test interpret
;; test run
;; target x86_64
;; target s390x
;; target aarch64
;; target riscv64
test run
set enable_heap_access_spectre_mitigation=true
target x86_64
target s390x
target aarch64
target riscv64
function %do_store(i64 vmctx, i64, i32) {
gv0 = vmctx
gv1 = load.i64 notrap aligned gv0+0

View File

@@ -1,14 +1,15 @@
;; !!! GENERATED BY 'make-heap-load-store-tests.sh' DO NOT EDIT !!!
test interpret
;; test run
;; target x86_64
;; target s390x
;; target aarch64
;; target riscv64
test run
set enable_heap_access_spectre_mitigation=false
target x86_64
target s390x
target aarch64
target riscv64
function %do_store(i64 vmctx, i32, i32) {
gv0 = vmctx
gv1 = load.i64 notrap aligned gv0+0

View File

@@ -1,14 +1,15 @@
;; !!! GENERATED BY 'make-heap-load-store-tests.sh' DO NOT EDIT !!!
test interpret
;; test run
;; target x86_64
;; target s390x
;; target aarch64
;; target riscv64
test run
set enable_heap_access_spectre_mitigation=true
target x86_64
target s390x
target aarch64
target riscv64
function %do_store(i64 vmctx, i32, i32) {
gv0 = vmctx
gv1 = load.i64 notrap aligned gv0+0

View File

@@ -1,14 +1,15 @@
;; !!! GENERATED BY 'make-heap-load-store-tests.sh' DO NOT EDIT !!!
test interpret
;; test run
;; target x86_64
;; target s390x
;; target aarch64
;; target riscv64
test run
set enable_heap_access_spectre_mitigation=false
target x86_64
target s390x
target aarch64
target riscv64
function %do_store(i64 vmctx, i32, i32) {
gv0 = vmctx
gv1 = load.i64 notrap aligned gv0+0

View File

@@ -1,14 +1,15 @@
;; !!! GENERATED BY 'make-heap-load-store-tests.sh' DO NOT EDIT !!!
test interpret
;; test run
;; target x86_64
;; target s390x
;; target aarch64
;; target riscv64
test run
set enable_heap_access_spectre_mitigation=true
target x86_64
target s390x
target aarch64
target riscv64
function %do_store(i64 vmctx, i32, i32) {
gv0 = vmctx
gv1 = load.i64 notrap aligned gv0+0

View File

@@ -1,14 +1,15 @@
;; !!! GENERATED BY 'make-heap-load-store-tests.sh' DO NOT EDIT !!!
test interpret
;; test run
;; target x86_64
;; target s390x
;; target aarch64
;; target riscv64
test run
set enable_heap_access_spectre_mitigation=false
target x86_64
target s390x
target aarch64
target riscv64
function %do_store(i64 vmctx, i64, i32) {
gv0 = vmctx
gv1 = load.i64 notrap aligned gv0+0

View File

@@ -1,14 +1,15 @@
;; !!! GENERATED BY 'make-heap-load-store-tests.sh' DO NOT EDIT !!!
test interpret
;; test run
;; target x86_64
;; target s390x
;; target aarch64
;; target riscv64
test run
set enable_heap_access_spectre_mitigation=true
target x86_64
target s390x
target aarch64
target riscv64
function %do_store(i64 vmctx, i64, i32) {
gv0 = vmctx
gv1 = load.i64 notrap aligned gv0+0

View File

@@ -1,14 +1,15 @@
;; !!! GENERATED BY 'make-heap-load-store-tests.sh' DO NOT EDIT !!!
test interpret
;; test run
;; target x86_64
;; target s390x
;; target aarch64
;; target riscv64
test run
set enable_heap_access_spectre_mitigation=false
target x86_64
target s390x
target aarch64
target riscv64
function %do_store(i64 vmctx, i64, i32) {
gv0 = vmctx
gv1 = load.i64 notrap aligned gv0+0

View File

@@ -1,14 +1,15 @@
;; !!! GENERATED BY 'make-heap-load-store-tests.sh' DO NOT EDIT !!!
test interpret
;; test run
;; target x86_64
;; target s390x
;; target aarch64
;; target riscv64
test run
set enable_heap_access_spectre_mitigation=true
target x86_64
target s390x
target aarch64
target riscv64
function %do_store(i64 vmctx, i64, i32) {
gv0 = vmctx
gv1 = load.i64 notrap aligned gv0+0

View File

@@ -39,14 +39,15 @@ function generate_one_test() {
;; !!! GENERATED BY 'make-heap-load-store-tests.sh' DO NOT EDIT !!!
test interpret
;; test run
;; target x86_64
;; target s390x
;; target aarch64
;; target riscv64
test run
set enable_heap_access_spectre_mitigation=${enable_spectre}
target x86_64
target s390x
target aarch64
target riscv64
function %do_store(i64 vmctx, ${index_type}, i32) {
gv0 = vmctx
gv1 = load.i64 notrap aligned gv0+0