diff --git a/lib/cretonne/meta/isa/__init__.py b/lib/cretonne/meta/isa/__init__.py
index 33b787f494..8f623d18bb 100644
--- a/lib/cretonne/meta/isa/__init__.py
+++ b/lib/cretonne/meta/isa/__init__.py
@@ -7,7 +7,7 @@ architecture supported by Cretonne.
 """
 from __future__ import absolute_import
 from cdsl.isa import TargetISA  # noqa
-from . import riscv
+from . import riscv, intel, arm32, arm64
 
 
 def all_isas():
@@ -16,4 +16,4 @@ def all_isas():
     Get a list of all the supported target ISAs. Each target ISA is represented
     as a :py:class:`cretonne.TargetISA` instance.
     """
-    return [riscv.ISA]
+    return [riscv.ISA, intel.ISA, arm32.ISA, arm64.ISA]
diff --git a/lib/cretonne/meta/isa/arm32/__init__.py b/lib/cretonne/meta/isa/arm32/__init__.py
new file mode 100644
index 0000000000..9c992d0c17
--- /dev/null
+++ b/lib/cretonne/meta/isa/arm32/__init__.py
@@ -0,0 +1,13 @@
+"""
+ARM 32-bit Architecture
+----------------------
+
+This target ISA generates code for ARMv7 and ARMv8 CPUs in 32-bit mode
+(AArch32). We support both ARM and Thumb2 instruction encodings.
+"""
+
+from __future__ import absolute_import
+from . import defs
+
+# Re-export the primary target ISA definition.
+ISA = defs.ISA.finish()
diff --git a/lib/cretonne/meta/isa/arm32/defs.py b/lib/cretonne/meta/isa/arm32/defs.py
new file mode 100644
index 0000000000..f90abc2001
--- /dev/null
+++ b/lib/cretonne/meta/isa/arm32/defs.py
@@ -0,0 +1,14 @@
+"""
+ARM 32-bit definitions.
+
+Commonly used definitions.
+"""
+from __future__ import absolute_import
+from cdsl.isa import TargetISA, CPUMode
+import base.instructions
+
+ISA = TargetISA('arm32', [base.instructions.GROUP])
+
+# CPU modes for 32-bit ARM and Thumb2.
+A32 = CPUMode('A32', ISA)
+T32 = CPUMode('T32', ISA)
diff --git a/lib/cretonne/meta/isa/arm64/__init__.py b/lib/cretonne/meta/isa/arm64/__init__.py
new file mode 100644
index 0000000000..198fc338b1
--- /dev/null
+++ b/lib/cretonne/meta/isa/arm64/__init__.py
@@ -0,0 +1,12 @@
+"""
+ARM 64-bit Architecture
+-----------------------
+
+ARMv8 CPUs running the Aarch64 architecture.
+"""
+
+from __future__ import absolute_import
+from . import defs
+
+# Re-export the primary target ISA definition.
+ISA = defs.ISA.finish()
diff --git a/lib/cretonne/meta/isa/arm64/defs.py b/lib/cretonne/meta/isa/arm64/defs.py
new file mode 100644
index 0000000000..e493b4424a
--- /dev/null
+++ b/lib/cretonne/meta/isa/arm64/defs.py
@@ -0,0 +1,11 @@
+"""
+ARM64 definitions.
+
+Commonly used definitions.
+"""
+from __future__ import absolute_import
+from cdsl.isa import TargetISA, CPUMode
+import base.instructions
+
+ISA = TargetISA('arm64', [base.instructions.GROUP])
+A64 = CPUMode('A64', ISA)
diff --git a/lib/cretonne/meta/isa/intel/__init__.py b/lib/cretonne/meta/isa/intel/__init__.py
new file mode 100644
index 0000000000..a97b424099
--- /dev/null
+++ b/lib/cretonne/meta/isa/intel/__init__.py
@@ -0,0 +1,22 @@
+"""
+Intel Target Architecture
+-------------------------
+
+This target ISA generates code for Intel CPUs with two separate CPU modes:
+
+`I32`
+    IA-32 architecture, also known as 'x86'. Generates code for the Intel 386
+    and later processors in 32-bit mode.
+`I64`
+    Intel 64 architecture, also known as 'x86-64, 'x64', and 'amd64'. Intel and
+    AMD CPUs running in 64-bit mode.
+
+Floating point is supported only on CPUs with support for SSE2 or later. There
+is no x87 floating point support.
+"""
+
+from __future__ import absolute_import
+from . import defs
+
+# Re-export the primary target ISA definition.
+ISA = defs.ISA.finish()
diff --git a/lib/cretonne/meta/isa/intel/defs.py b/lib/cretonne/meta/isa/intel/defs.py
new file mode 100644
index 0000000000..50251b44af
--- /dev/null
+++ b/lib/cretonne/meta/isa/intel/defs.py
@@ -0,0 +1,14 @@
+"""
+Intel definitions.
+
+Commonly used definitions.
+"""
+from __future__ import absolute_import
+from cdsl.isa import TargetISA, CPUMode
+import base.instructions
+
+ISA = TargetISA('intel', [base.instructions.GROUP])
+
+# CPU modes for 32-bit and 64-bit operation.
+I32 = CPUMode('I32', ISA)
+I64 = CPUMode('I64', ISA)