Only save callee-saved registers that are used (#293)
* Only save callee-saved registers that are actually being used. * Rename AllocatableSet to RegisterSet * Style cleanup and small renames for readability. * Adjust x86 prologue-epilogue test to account for callee-saved register optimization. * Add more tests for prologue-epilogue optimizations.
This commit is contained in:
Tyler McMullen
committed by
Dan Gohman
Dan Gohman
parent
0948ca9963
commit
775c674b38
@@ -3,30 +3,206 @@ set is_64bit
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set is_compressed
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isa intel haswell
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function %foo() {
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; An empty function.
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function %empty() {
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ebb0:
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return
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}
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; check: function %empty(i64 fp [%rbp]) -> i64 fp [%rbp] system_v {
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; nextln: ss0 = incoming_arg 16, offset -16
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; nextln:
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; nextln: ebb0(v0: i64 [%rbp]):
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; nextln: x86_push v0
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; nextln: copy_special %rsp -> %rbp
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; nextln: v1 = x86_pop.i64
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; nextln: return v1
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; nextln: }
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; A function with a single stack slot.
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function %one_stack_slot() {
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ss0 = explicit_slot 168
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ebb0:
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return
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}
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; check: function %foo(i64 fp [%rbp], i64 csr [%rbx], i64 csr [%r12], i64 csr [%r13], i64 csr [%r14], i64 csr [%r15]) -> i64 fp [%rbp], i64 csr [%rbx], i64 csr [%r12], i64 csr [%r13], i64 csr [%r14], i64 csr [%r15] system_v {
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; nextln: ss0 = explicit_slot 168, offset -224
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; nextln: ss1 = incoming_arg 56, offset -56
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; check: ebb0(v0: i64 [%rbp], v1: i64 [%rbx], v2: i64 [%r12], v3: i64 [%r13], v4: i64 [%r14], v5: i64 [%r15]):
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; check: function %one_stack_slot(i64 fp [%rbp]) -> i64 fp [%rbp] system_v {
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; nextln: ss0 = explicit_slot 168, offset -184
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; nextln: ss1 = incoming_arg 16, offset -16
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; nextln:
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; nextln: ebb0(v0: i64 [%rbp]):
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; nextln: x86_push v0
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; nextln: copy_special %rsp -> %rbp
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; nextln: x86_push v1
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; nextln: x86_push v2
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; nextln: x86_push v3
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; nextln: x86_push v4
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; nextln: x86_push v5
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; nextln: adjust_sp_imm -168
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; nextln: adjust_sp_imm 168
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; nextln: v11 = x86_pop.i64
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; nextln: v10 = x86_pop.i64
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; nextln: v9 = x86_pop.i64
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; nextln: v8 = x86_pop.i64
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; nextln: v7 = x86_pop.i64
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; nextln: v6 = x86_pop.i64
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; nextln: return v6, v7, v8, v9, v10, v11
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; nextln: adjust_sp_imm -176
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; nextln: adjust_sp_imm 176
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; nextln: v1 = x86_pop.i64
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; nextln: return v1
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; nextln: }
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; A function performing a call.
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function %call() {
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fn0 = function %foo()
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ebb0:
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call fn0()
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return
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}
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; check: function %call(i64 fp [%rbp]) -> i64 fp [%rbp] system_v {
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; nextln: ss0 = incoming_arg 16, offset -16
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; nextln: sig0 = () system_v
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; nextln: fn0 = sig0 %foo
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; nextln:
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; nextln: ebb0(v0: i64 [%rbp]):
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; nextln: x86_push v0
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; nextln: copy_special %rsp -> %rbp
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; nextln: call fn0()
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; nextln: v1 = x86_pop.i64
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; nextln: return v1
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; nextln: }
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; A function that uses a lot of registers but doesn't quite need to spill.
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function %no_spill(i64, i64) {
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ebb0(v0: i64, v1: i64):
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v2 = load.i32 v0+0
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v3 = load.i32 v0+8
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v4 = load.i32 v0+16
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v5 = load.i32 v0+24
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v6 = load.i32 v0+32
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v7 = load.i32 v0+40
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v8 = load.i32 v0+48
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v9 = load.i32 v0+56
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v10 = load.i32 v0+64
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v11 = load.i32 v0+72
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v12 = load.i32 v0+80
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v13 = load.i32 v0+88
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v14 = load.i32 v0+96
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store.i32 v2, v1+0
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store.i32 v3, v1+8
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store.i32 v4, v1+16
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store.i32 v5, v1+24
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store.i32 v6, v1+32
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store.i32 v7, v1+40
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store.i32 v8, v1+48
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store.i32 v9, v1+56
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store.i32 v10, v1+64
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store.i32 v11, v1+72
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store.i32 v12, v1+80
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store.i32 v13, v1+88
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store.i32 v14, v1+96
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return
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}
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; check: function %no_spill(i64 [%rdi], i64 [%rsi], i64 fp [%rbp], i64 csr [%rbx], i64 csr [%r12], i64 csr [%r13], i64 csr [%r14], i64 csr [%r15]) -> i64 fp [%rbp], i64 csr [%rbx], i64 csr [%r12], i64 csr [%r13], i64 csr [%r14], i64 csr [%r15] system_v {
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; nextln: ss0 = incoming_arg 56, offset -56
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; nextln:
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; nextln: ebb0(v0: i64 [%rdi], v1: i64 [%rsi], v15: i64 [%rbp], v16: i64 [%rbx], v17: i64 [%r12], v18: i64 [%r13], v19: i64 [%r14], v20: i64 [%r15]):
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; nextln: x86_push v15
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; nextln: copy_special %rsp -> %rbp
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; nextln: x86_push v16
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; nextln: x86_push v17
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; nextln: x86_push v18
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; nextln: x86_push v19
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; nextln: x86_push v20
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; nextln: adjust_sp_imm -8
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; nextln: v2 = load.i32 v0
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; nextln: v3 = load.i32 v0+8
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; nextln: v4 = load.i32 v0+16
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; nextln: v5 = load.i32 v0+24
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; nextln: v6 = load.i32 v0+32
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; nextln: v7 = load.i32 v0+40
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; nextln: v8 = load.i32 v0+48
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; nextln: v9 = load.i32 v0+56
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; nextln: v10 = load.i32 v0+64
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; nextln: v11 = load.i32 v0+72
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; nextln: v12 = load.i32 v0+80
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; nextln: v13 = load.i32 v0+88
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; nextln: v14 = load.i32 v0+96
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; nextln: store v2, v1
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; nextln: store v3, v1+8
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; nextln: store v4, v1+16
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; nextln: store v5, v1+24
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; nextln: store v6, v1+32
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; nextln: store v7, v1+40
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; nextln: store v8, v1+48
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; nextln: store v9, v1+56
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; nextln: store v10, v1+64
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; nextln: store v11, v1+72
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; nextln: store v12, v1+80
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; nextln: store v13, v1+88
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; nextln: store v14, v1+96
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; nextln: adjust_sp_imm 8
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; nextln: v26 = x86_pop.i64
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; nextln: v25 = x86_pop.i64
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; nextln: v24 = x86_pop.i64
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; nextln: v23 = x86_pop.i64
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; nextln: v22 = x86_pop.i64
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; nextln: v21 = x86_pop.i64
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; nextln: return v21, v22, v23, v24, v25, v26
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; nextln: }
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; This function requires too many registers and must spill.
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function %yes_spill(i64, i64) {
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ebb0(v0: i64, v1: i64):
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v2 = load.i32 v0+0
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v3 = load.i32 v0+8
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v4 = load.i32 v0+16
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v5 = load.i32 v0+24
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v6 = load.i32 v0+32
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v7 = load.i32 v0+40
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v8 = load.i32 v0+48
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v9 = load.i32 v0+56
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v10 = load.i32 v0+64
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v11 = load.i32 v0+72
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v12 = load.i32 v0+80
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v13 = load.i32 v0+88
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v14 = load.i32 v0+96
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v15 = load.i32 v0+104
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store.i32 v2, v1+0
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store.i32 v3, v1+8
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store.i32 v4, v1+16
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store.i32 v5, v1+24
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store.i32 v6, v1+32
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store.i32 v7, v1+40
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store.i32 v8, v1+48
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store.i32 v9, v1+56
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store.i32 v10, v1+64
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store.i32 v11, v1+72
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store.i32 v12, v1+80
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store.i32 v13, v1+88
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store.i32 v14, v1+96
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store.i32 v15, v1+104
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return
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}
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; check: function %yes_spill(i64 [%rdi], i64 [%rsi], i64 fp [%rbp], i64 csr [%rbx], i64 csr [%r12], i64 csr [%r13], i64 csr [%r14], i64 csr [%r15]) -> i64 fp [%rbp], i64 csr [%rbx], i64 csr [%r12], i64 csr [%r13], i64 csr [%r14], i64 csr [%r15] system_v {
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; check: ss0 = spill_slot
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; check: ebb0(v16: i64 [%rdi], v17: i64 [%rsi], v48: i64 [%rbp], v49: i64 [%rbx], v50: i64 [%r12], v51: i64 [%r13], v52: i64 [%r14], v53: i64 [%r15]):
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; nextln: x86_push v48
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; nextln: copy_special %rsp -> %rbp
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; nextln: x86_push v49
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; nextln: x86_push v50
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; nextln: x86_push v51
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; nextln: x86_push v52
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; nextln: x86_push v53
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; nextln: adjust_sp_imm
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; check: spill
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; check: fill
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; check: adjust_sp_imm
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; nextln: v59 = x86_pop.i64
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; nextln: v58 = x86_pop.i64
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; nextln: v57 = x86_pop.i64
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; nextln: v56 = x86_pop.i64
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; nextln: v55 = x86_pop.i64
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; nextln: v54 = x86_pop.i64
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; nextln: return v54, v55, v56, v57, v58, v59
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; nextln: }
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