T0b1/wasmtime
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Add x86_pblendw instruction

Browse Source 
This instruction is necessary for lowering `fcvt_from_uint`.
This commit is contained in:
Andrew Brown
2020-05-26 14:12:25 -07:00
parent 546fc9ddf1
commit 772ce73f7f
5 changed files with 35 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
cranelift/codegen/meta/src/isa/x86/encodings.rs
View File

@@ -1639,6 +1639,7 @@ fn define_simd(
let x86_movlhps = x86.by_name("x86_movlhps");
let x86_movsd = x86.by_name("x86_movsd");
let x86_packss = x86.by_name("x86_packss");
let x86_pblendw = x86.by_name("x86_pblendw");
let x86_pextr = x86.by_name("x86_pextr");
let x86_pinsr = x86.by_name("x86_pinsr");
let x86_pmaxs = x86.by_name("x86_pmaxs");
@@ -1744,6 +1745,13 @@ fn define_simd(
e.enc_both_inferred_maybe_isap(instruction, template, Some(use_sse41_simd));
}
// PBLENDW, select lanes using a u8 immediate.
for ty in ValueType::all_lane_types().filter(|t| t.lane_bits() == 16) {
let instruction = x86_pblendw.bind(vector(ty, sse_vector_size));
let template = rec_fa_ib.opcodes(&PBLENDW);
e.enc_both_inferred_maybe_isap(instruction, template, Some(use_sse41_simd));
}
// SIMD scalar_to_vector; this uses MOV to copy the scalar value to an XMM register; according
// to the Intel manual: "When the destination operand is an XMM register, the source operand is
// written to the low doubleword of the register and the register is zero-extended to 128 bits."