moved crates in lib/ to src/, renamed crates, modified some files' text (#660)

moved crates in lib/ to src/, renamed crates, modified some files' text (#660)

cranelift/filetests/filetests/postopt/basic.clif

@@ -0,0 +1,100 @@
+test postopt
+target i686
+
+; Test that compare+branch sequences are folded effectively on x86.
+
+function %br_icmp(i32, i32) -> i32 {
+ebb0(v0: i32, v1: i32):
+[Op1icscc#39,%rdx]  v2 = icmp slt v0, v1
+[Op1t8jccd_long#85] brnz v2, ebb1
+[Op1ret#c3]         return v1
+
+ebb1:
+[Op1pu_id#b8,%rax]  v8 = iconst.i32 3
+[Op1ret#c3]         return v8
+}
+; sameln: function %br_icmp
+; nextln: ebb0(v0: i32, v1: i32):
+; nextln:    v9 = ifcmp v0, v1
+; nextln:    v2 = trueif slt v9
+; nextln:    brif slt v9, ebb1
+; nextln:    return v1
+; nextln: 
+; nextln: ebb1:
+; nextln:    v8 = iconst.i32 3
+; nextln:    return v8
+; nextln: }
+
+; Use brz instead of brnz, so the condition is inverted.
+
+function %br_icmp_inverse(i32, i32) -> i32 {
+ebb0(v0: i32, v1: i32):
+[Op1icscc#39,%rdx]  v2 = icmp slt v0, v1
+[Op1t8jccd_long#84] brz v2, ebb1
+[Op1ret#c3]         return v1
+
+ebb1:
+[Op1pu_id#b8,%rax]  v8 = iconst.i32 3
+[Op1ret#c3]         return v8
+}
+; sameln: function %br_icmp_inverse
+; nextln: ebb0(v0: i32, v1: i32):
+; nextln:    v9 = ifcmp v0, v1
+; nextln:    v2 = trueif slt v9
+; nextln:    brif sge v9, ebb1
+; nextln:    return v1
+; nextln: 
+; nextln: ebb1:
+; nextln:    v8 = iconst.i32 3
+; nextln:    return v8
+; nextln: }
+
+; Use icmp_imm instead of icmp.
+
+function %br_icmp_imm(i32, i32) -> i32 {
+ebb0(v0: i32, v1: i32):
+[Op1icscc_ib#7083]  v2 = icmp_imm slt v0, 2
+[Op1t8jccd_long#84] brz v2, ebb1
+[Op1ret#c3]         return v1
+
+ebb1:
+[Op1pu_id#b8,%rax]  v8 = iconst.i32 3
+[Op1ret#c3]         return v8
+}
+; sameln: function %br_icmp_imm
+; nextln: ebb0(v0: i32, v1: i32):
+; nextln:    v9 = ifcmp_imm v0, 2
+; nextln:    v2 = trueif slt v9
+; nextln:    brif sge v9, ebb1
+; nextln:    return v1
+; nextln: 
+; nextln: ebb1:
+; nextln:    v8 = iconst.i32 3
+; nextln:    return v8
+; nextln: }
+
+; Use fcmp instead of icmp.
+
+function %br_fcmp(f32, f32) -> f32 {
+ebb0(v0: f32, v1: f32):
+[Op2fcscc#42e,%rdx] v2 = fcmp gt v0, v1
+[Op1t8jccd_long#84] brz v2, ebb1
+[Op1ret#c3]         return v1
+
+ebb1:
+[Op1pu_id#b8,%rax]   v18 = iconst.i32 0x40a8_0000
+[Mp2frurm#56e,%xmm0] v8 = bitcast.f32 v18
+[Op1ret#c3]         return v8
+}
+; sameln: function %br_fcmp
+; nextln: ebb0(v0: f32, v1: f32):
+; nextln:    v19 = ffcmp v0, v1
+; nextln:    v2 = trueff gt v19
+; nextln:    brff ule v19, ebb1
+; nextln:    return v1
+; nextln: 
+; nextln: ebb1:
+; nextln:    v18 = iconst.i32 0x40a8_0000
+; nextln:    v8 = bitcast.f32 v18
+; nextln:    return v8
+; nextln: }

cranelift/filetests/filetests/postopt/complex_memory_ops.clif

@@ -0,0 +1,94 @@
+test postopt
+target x86_64
+
+function %dual_loads(i64, i64) -> i64 {
+ebb0(v0: i64, v1: i64):
+[RexOp1rr#8001]    v3 = iadd v0, v1
+                   v4 = load.i64 v3
+                   v5 = uload8.i64 v3
+                   v6 = sload8.i64 v3
+                   v7 = uload16.i64 v3
+                   v8 = sload16.i64 v3
+                   v9 = uload32.i64 v3
+                   v10 = sload32.i64 v3
+[Op1ret#c3]        return v10
+}
+
+; sameln: function %dual_loads
+; nextln: ebb0(v0: i64, v1: i64):
+; nextln:    v3 = iadd v0, v1
+; nextln:    v4 = load_complex.i64 v0+v1
+; nextln:    v5 = uload8_complex.i64 v0+v1
+; nextln:    v6 = sload8_complex.i64 v0+v1
+; nextln:    v7 = uload16_complex.i64 v0+v1
+; nextln:    v8 = sload16_complex.i64 v0+v1
+; nextln:    v9 = uload32_complex v0+v1
+; nextln:    v10 = sload32_complex v0+v1
+; nextln:    return v10
+; nextln: }
+
+function %dual_loads2(i64, i64) -> i64 {
+ebb0(v0: i64, v1: i64):
+[RexOp1rr#8001]    v3 = iadd v0, v1
+                   v4 = load.i64 v3+1
+                   v5 = uload8.i64 v3+1
+                   v6 = sload8.i64 v3+1
+                   v7 = uload16.i64 v3+1
+                   v8 = sload16.i64 v3+1
+                   v9 = uload32.i64 v3+1
+                   v10 = sload32.i64 v3+1
+[Op1ret#c3]        return v10
+}
+
+; sameln: function %dual_loads2
+; nextln: ebb0(v0: i64, v1: i64):
+; nextln:    v3 = iadd v0, v1
+; nextln:    v4 = load_complex.i64 v0+v1+1
+; nextln:    v5 = uload8_complex.i64 v0+v1+1
+; nextln:    v6 = sload8_complex.i64 v0+v1+1
+; nextln:    v7 = uload16_complex.i64 v0+v1+1
+; nextln:    v8 = sload16_complex.i64 v0+v1+1
+; nextln:    v9 = uload32_complex v0+v1+1
+; nextln:    v10 = sload32_complex v0+v1+1
+; nextln:    return v10
+; nextln: }
+
+function %dual_stores(i64, i64, i64) {
+ebb0(v0: i64, v1: i64, v2: i64):
+[RexOp1rr#8001]    v3 = iadd v0, v1
+[RexOp1st#8089]    store.i64 v2, v3
+[RexOp1st#88]      istore8.i64 v2, v3
+[RexMp1st#189]     istore16.i64 v2, v3
+[RexOp1st#89]      istore32.i64 v2, v3
+[Op1ret#c3]        return
+}
+
+; sameln: function %dual_stores
+; nextln: ebb0(v0: i64, v1: i64, v2: i64):
+; nextln:    v3 = iadd v0, v1
+; nextln:    store_complex v2, v0+v1
+; nextln:    istore8_complex v2, v0+v1
+; nextln:    istore16_complex v2, v0+v1
+; nextln:    istore32_complex v2, v0+v1
+; nextln:    return
+; nextln: }
+
+function %dual_stores2(i64, i64, i64) {
+ebb0(v0: i64, v1: i64, v2: i64):
+[RexOp1rr#8001]         v3 = iadd v0, v1
+[RexOp1stDisp8#8089]    store.i64 v2, v3+1
+[RexOp1stDisp8#88]      istore8.i64 v2, v3+1
+[RexMp1stDisp8#189]     istore16.i64 v2, v3+1
+[RexOp1stDisp8#89]      istore32.i64 v2, v3+1
+[Op1ret#c3]             return
+}
+
+; sameln: function %dual_stores2
+; nextln: ebb0(v0: i64, v1: i64, v2: i64):
+; nextln:    v3 = iadd v0, v1
+; nextln:    store_complex v2, v0+v1+1
+; nextln:    istore8_complex v2, v0+v1+1
+; nextln:    istore16_complex v2, v0+v1+1
+; nextln:    istore32_complex v2, v0+v1+1
+; nextln:    return
+; nextln: }

cranelift/filetests/filetests/postopt/fold_offset_into_address.clif

@@ -0,0 +1,32 @@
+test postopt
+target x86_64
+
+; Fold the immediate of an iadd_imm into an address offset.
+
+function u0:0(i64 vmctx) -> i64 {
+ebb0(v0: i64):
+                     v1 = iadd_imm.i64 v0, 16
+[RexOp1ldDisp8#808b] v2 = load.i64 notrap aligned v1
+[Op1ret#c3]          return v2
+}
+
+; sameln: function u0:0(i64 vmctx) -> i64 fast {
+; nextln: ebb0(v0: i64):
+; nextln:                                     v1 = iadd_imm v0, 16
+; nextln: [RexOp1ldDisp8#808b]                v2 = load.i64 notrap aligned v0+16
+; nextln: [Op1ret#c3]                         return v2
+; nextln: }
+
+function u0:1(i64, i64 vmctx) {
+ebb0(v3: i64, v0: i64):
+                     v1 = iadd_imm.i64 v0, 16
+[RexOp1stDisp8#8089] store.i64 notrap aligned v3, v1
+[Op1ret#c3]          return
+}
+
+; sameln: function u0:1(i64, i64 vmctx) fast {
+; nextln: ebb0(v3: i64, v0: i64):
+; nextln:                                     v1 = iadd_imm v0, 16
+; nextln: [RexOp1stDisp8#8089]                store notrap aligned v3, v0+16
+; nextln: [Op1ret#c3]                         return
+; nextln: }