moved crates in lib/ to src/, renamed crates, modified some files' text (#660)

moved crates in lib/ to src/, renamed crates, modified some files' text (#660)

cranelift/filetests/filetests/licm/basic.clif

@@ -0,0 +1,35 @@
+test licm
+target riscv32
+
+function %simple_loop(i32) -> i32 {
+
+ebb0(v0: i32):
+    jump ebb1(v0)
+
+ebb1(v1: i32):
+    v2 = iconst.i32 1
+    v3 = iconst.i32 2
+    v4 = iadd v2, v3
+    brz v1, ebb2(v1)
+    v5 = isub v1, v2
+    jump ebb1(v5)
+
+ebb2(v6: i32):
+    return v6
+
+}
+; sameln: function %simple_loop
+; nextln: ebb0(v0: i32):
+; nextln:     v2 = iconst.i32 1
+; nextln:     v3 = iconst.i32 2
+; nextln:     v4 = iadd v2, v3
+; nextln:     jump ebb1(v0)
+; nextln: 
+; nextln: ebb1(v1: i32):
+; nextln:     brz v1, ebb2(v1)
+; nextln:     v5 = isub v1, v2
+; nextln:     jump ebb1(v5)
+; nextln: 
+; nextln: ebb2(v6: i32):
+; nextln:     return v6
+; nextln: }

cranelift/filetests/filetests/licm/complex.clif

@@ -0,0 +1,90 @@
+test licm
+target riscv32
+
+function %complex(i32) -> i32 system_v {
+ebb0(v0: i32):
+[UJ#1b]    jump ebb1(v0)
+
+         ebb1(v1: i32):
+            v2 = iconst.i32 1
+            v3 = iconst.i32 4
+            v4 = iadd v2, v1
+[SBzero#18] brz v1, ebb2(v2)
+[UJ#1b]     jump ebb4(v4)
+
+         ebb2(v5: i32):
+            v6 = iconst.i32 2
+            v7 = iadd v5, v4
+            v8 = iadd v6, v1
+[UJ#1b]   jump ebb3(v8)
+
+         ebb3(v9: i32):
+            v10 = iadd v9, v5
+            v11 = iadd.i32 v1, v4
+[SBzero#18] brz.i32 v1, ebb2(v9)
+[UJ#1b]   jump ebb6(v10)
+
+         ebb4(v12: i32):
+            v13 = iconst.i32 3
+            v14 = iadd v12, v13
+            v15 = iadd.i32 v4, v13
+[UJ#1b]   jump ebb5(v13)
+
+         ebb5(v16: i32):
+            v17 = iadd.i32 v14, v4
+[SBzero#18] brz.i32 v1, ebb4(v16)
+[UJ#1b]   jump ebb6(v16)
+
+         ebb6(v18: i32):
+            v19 = iadd v18, v2
+            v20 = iadd.i32 v2, v3
+[SBzero#18] brz.i32 v1, ebb1(v20)
+[Iret#19]   return v19
+}
+
+; sameln: function %complex
+; nextln: ebb0(v0: i32):
+; nextln:     v2 = iconst.i32 1
+; nextln:     v3 = iconst.i32 4
+; nextln:     v6 = iconst.i32 2
+; nextln:     v13 = iconst.i32 3
+; nextln:     v20 = iadd v2, v3
+; nextln:     jump ebb1(v0)
+; nextln: 
+; nextln: ebb1(v1: i32):
+; nextln:     v4 = iadd.i32 v2, v1
+; nextln:     brz v1, ebb7(v2)
+; nextln:     jump ebb8(v4)
+; nextln: 
+; nextln: ebb7(v21: i32):
+; nextln:     v8 = iadd.i32 v6, v1
+; nextln:     v11 = iadd.i32 v1, v4
+; nextln:     jump ebb2(v21)
+; nextln: 
+; nextln: ebb2(v5: i32):
+; nextln:     v7 = iadd v5, v4
+; nextln:     jump ebb3(v8)
+; nextln: 
+; nextln: ebb3(v9: i32):
+; nextln:     v10 = iadd v9, v5
+; nextln:     brz.i32 v1, ebb2(v9)
+; nextln:     jump ebb6(v10)
+; nextln: 
+; nextln: ebb8(v22: i32):
+; nextln:     v15 = iadd.i32 v4, v13
+; nextln:     jump ebb4(v22)
+; nextln: 
+; nextln: ebb4(v12: i32):
+; nextln:     v14 = iadd v12, v13
+; nextln:     jump ebb5(v13)
+; nextln: 
+; nextln: ebb5(v16: i32):
+; nextln:     v17 = iadd.i32 v14, v4
+; nextln:     brz.i32 v1, ebb4(v16)
+; nextln:     jump ebb6(v16)
+; nextln: 
+; nextln: ebb6(v18: i32):
+; nextln:     v19 = iadd v18, v2
+; nextln:     brz.i32 v1, ebb1(v20)
+; nextln:     return v19
+; nextln: }

cranelift/filetests/filetests/licm/critical-edge.clif

@@ -0,0 +1,42 @@
+test licm
+target riscv32
+
+; The loop in this function is entered from a critical edge.
+
+function %critical_edge(i32, i32) -> i32 {
+
+            ebb0(v0: i32, v7: i32):
+[SBzero#38]   brnz v7, ebb1(v0)
+[Iret#19]     return v0
+
+            ebb1(v1: i32):
+              v2 = iconst.i32 1
+              v3 = iconst.i32 2
+              v4 = iadd v2, v3
+[SBzero#18]   brz v1, ebb2(v1)
+              v5 = isub v1, v2
+[UJ#1b]       jump ebb1(v5)
+
+            ebb2(v6: i32):
+[Iret#19]     return v6
+
+}
+; sameln: function %critical_edge
+; nextln: ebb0(v0: i32, v7: i32):
+; nextln:     brnz v7, ebb3(v0)
+; nextln:     return v0
+; nextln: 
+; nextln: ebb3(v8: i32):
+; nextln:     v2 = iconst.i32 1
+; nextln:     v3 = iconst.i32 2
+; nextln:     v4 = iadd v2, v3
+; nextln:     jump ebb1(v8)
+; nextln: 
+; nextln: ebb1(v1: i32):
+; nextln:     brz v1, ebb2(v1)
+; nextln:     v5 = isub v1, v2
+; nextln:     jump ebb1(v5)
+; nextln: 
+; nextln: ebb2(v6: i32):
+; nextln:     return v6
+; nextln: }

cranelift/filetests/filetests/licm/encoding.clif

@@ -0,0 +1,36 @@
+test licm
+target riscv32
+
+; Ensure that instructions emitted by LICM get encodings.
+
+function %simple_loop(i32) -> i32 {
+            ebb0(v0: i32):
+[UJ#1b]       jump ebb1(v0)
+
+            ebb1(v1: i32):
+[Iz#04,%x0]   v2 = iconst.i32 1
+[Iz#04,%x1]   v3 = iconst.i32 2
+[R#0c,%x2]    v4 = iadd v2, v3
+[SBzero#18]   brz v1, ebb2(v1)
+[R#200c,%x5]  v5 = isub v1, v2
+[UJ#1b]       jump ebb1(v5)
+
+            ebb2(v6: i32):
+[Iret#19]     return v6
+}
+
+; check: function
+; nextln:                                 ebb0(v0: i32):
+; nextln: [Iz#04,%x0]                         v2 = iconst.i32 1
+; nextln: [Iz#04,%x1]                         v3 = iconst.i32 2
+; nextln: [R#0c,%x2]                          v4 = iadd v2, v3
+; nextln: [UJ#1b]                             jump ebb1(v0)
+; nextln: 
+; nextln:                                 ebb1(v1: i32):
+; nextln: [SBzero#18]                         brz v1, ebb2(v1)
+; nextln: [R#200c,%x5]                        v5 = isub v1, v2
+; nextln: [UJ#1b]                             jump ebb1(v5)
+; nextln: 
+; nextln:                                 ebb2(v6: i32):
+; nextln: [Iret#19]                           return v6
+; nextln: }

cranelift/filetests/filetests/licm/multiple-blocks.clif

@@ -0,0 +1,47 @@
+test licm
+target riscv32
+
+function %multiple_blocks(i32) -> i32 {
+
+ebb0(v0: i32):
+    jump ebb1(v0)
+
+ebb1(v10: i32):
+    v11 = iconst.i32 1
+    v12 = iconst.i32 2
+    v13 = iadd v11, v12
+    brz v10, ebb2(v10)
+    v15 = isub v10, v11
+    brz v15, ebb3(v15)
+    v14 = isub v10, v11
+    jump ebb1(v14)
+
+ebb2(v20: i32):
+    return v20
+
+ebb3(v30: i32):
+    v31 = iadd v11, v13
+    jump ebb1(v30)
+
+}
+; sameln:function %multiple_blocks(i32) -> i32 {
+; nextln: ebb0(v0: i32):
+; nextln:     v11 = iconst.i32 1
+; nextln:     v12 = iconst.i32 2
+; nextln:     v13 = iadd v11, v12
+; nextln:     v31 = iadd v11, v13
+; nextln:     jump ebb1(v0)
+; nextln: 
+; nextln: ebb1(v10: i32):
+; nextln:     brz v10, ebb2(v10)
+; nextln:     v15 = isub v10, v11
+; nextln:     brz v15, ebb3(v15)
+; nextln:     v14 = isub v10, v11
+; nextln:     jump ebb1(v14)
+; nextln: 
+; nextln: ebb2(v20: i32):
+; nextln:     return v20
+; nextln: 
+; nextln: ebb3(v30: i32):
+; nextln:     jump ebb1(v30)
+; nextln: }

cranelift/filetests/filetests/licm/nested_loops.clif

@@ -0,0 +1,56 @@
+test licm
+target riscv32
+
+function %nested_loops(i32) -> i32 {
+
+ebb0(v0: i32):
+    jump ebb1(v0)
+
+ebb1(v1: i32):
+    v2 = iconst.i32 1
+    v3 = iconst.i32 2
+    v4 = iadd v2, v3
+    v5 = isub v1, v2
+    jump ebb2(v5, v5)
+
+ebb2(v10: i32, v11: i32):
+    brz v11, ebb3(v10)
+    v12 = iconst.i32 1
+    v15 = iadd v12, v5
+    v13 = isub v11, v12
+    jump ebb2(v10,v13)
+
+ebb3(v20: i32):
+    brz v20, ebb4(v20)
+    jump ebb1(v20)
+
+ebb4(v30: i32):
+    return v30
+
+}
+
+; sameln:function %nested_loops(i32) -> i32 {
+; nextln: ebb0(v0: i32):
+; nextln:     v2 = iconst.i32 1
+; nextln:     v3 = iconst.i32 2
+; nextln:     v4 = iadd v2, v3
+; nextln:     v12 = iconst.i32 1
+; nextln:     jump ebb1(v0)
+; nextln: 
+; nextln: ebb1(v1: i32):
+; nextln:     v5 = isub v1, v2
+; nextln:     v15 = iadd.i32 v12, v5
+; nextln:     jump ebb2(v5, v5)
+; nextln: 
+; nextln: ebb2(v10: i32, v11: i32):
+; nextln:     brz v11, ebb3(v10)
+; nextln:     v13 = isub v11, v12
+; nextln:     jump ebb2(v10, v13)
+; nextln: 
+; nextln: ebb3(v20: i32):
+; nextln:     brz v20, ebb4(v20)
+; nextln:     jump ebb1(v20)
+; nextln: 
+; nextln: ebb4(v30: i32):
+; nextln:     return v30
+; nextln: }

cranelift/filetests/filetests/licm/reject.clif

@@ -0,0 +1,82 @@
+test licm
+target riscv32
+
+function %other_side_effects(i32) -> i32 {
+
+ebb0(v0: i32):
+    jump ebb1(v0)
+
+ebb1(v1: i32):
+    regmove.i32 v0, %x10 -> %x20
+; check: ebb1(v1: i32):
+; check: regmove.i32 v0, %x10 -> %x20
+    v2 = iconst.i32 1
+    brz v1, ebb2(v1)
+    v5 = isub v1, v2
+    jump ebb1(v5)
+
+ebb2(v6: i32):
+    return v6
+
+}
+
+function %cpu_flags(i32, i32) -> i32 {
+ebb0(v0: i32, v1: i32):
+    jump ebb1(v0, v1)
+
+ebb1(v2: i32, v3: i32):
+    v4 = ifcmp.i32 v0, v1
+    v5 = selectif.i32 eq v4, v2, v3
+; check: ebb1(v2: i32, v3: i32):
+; check: ifcmp.i32 v0, v1
+; check: v5 = selectif.i32 eq v4, v2, v3
+    v8 = iconst.i32 1
+    brz v1, ebb2(v1)
+    v9 = isub v1, v8
+    v10 = iadd v1, v8
+    jump ebb1(v9, v10)
+
+ebb2(v6: i32):
+    return v6
+}
+
+function %spill(i32, i32) -> i32 {
+ebb0(v0: i32, v1: i32):
+    v2 = spill.i32 v0
+    jump ebb1(v0, v1)
+
+ebb1(v3: i32, v4: i32):
+    v5 = spill.i32 v1
+    v6 = fill.i32 v2
+    v7 = fill.i32 v5
+; check: ebb1(v3: i32, v4: i32):
+; check: v5 = spill.i32 v1
+; check: v6 = fill.i32 v2
+; check: v7 = fill v5
+    brz v1, ebb2(v1)
+    v9 = isub v1, v4
+    jump ebb1(v9, v3)
+
+ebb2(v10: i32):
+    return v10
+}
+
+function %non_invariant_aliases(i32) -> i32 {
+
+ebb0(v0: i32):
+    jump ebb1(v0)
+
+ebb1(v1: i32):
+    v8 -> v1
+    v9 -> v1
+    v2 = iadd v8, v9
+; check: ebb1(v1: i32):
+; check: v2 = iadd v8, v9
+    brz v1, ebb2(v1)
+    v5 = isub v1, v2
+    jump ebb1(v5)
+
+ebb2(v6: i32):
+    return v6
+
+}