moved crates in lib/ to src/, renamed crates, modified some files' text (#660)
moved crates in lib/ to src/, renamed crates, modified some files' text (#660)
This commit is contained in:
lazypassion
385
cranelift/codegen/src/postopt.rs
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385
cranelift/codegen/src/postopt.rs
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@@ -0,0 +1,385 @@
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//! A post-legalization rewriting pass.
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#![allow(non_snake_case)]
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use crate::cursor::{Cursor, EncCursor};
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use crate::ir::condcodes::{CondCode, FloatCC, IntCC};
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use crate::ir::dfg::ValueDef;
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use crate::ir::immediates::{Imm64, Offset32};
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use crate::ir::instructions::{Opcode, ValueList};
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use crate::ir::{Ebb, Function, Inst, InstBuilder, InstructionData, MemFlags, Type, Value};
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use crate::isa::TargetIsa;
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use crate::timing;
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/// Information collected about a compare+branch sequence.
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struct CmpBrInfo {
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/// The branch instruction.
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br_inst: Inst,
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/// The icmp, icmp_imm, or fcmp instruction.
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cmp_inst: Inst,
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/// The destination of the branch.
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destination: Ebb,
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/// The arguments of the branch.
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args: ValueList,
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/// The first argument to the comparison. The second is in the `kind` field.
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cmp_arg: Value,
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/// If the branch is `brz` rather than `brnz`, we need to invert the condition
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/// before the branch.
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invert_branch_cond: bool,
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/// The kind of comparison, and the second argument.
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kind: CmpBrKind,
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}
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enum CmpBrKind {
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Icmp { cond: IntCC, arg: Value },
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IcmpImm { cond: IntCC, imm: Imm64 },
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Fcmp { cond: FloatCC, arg: Value },
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}
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/// Optimize comparisons to use flags values, to avoid materializing conditions
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/// in integer registers.
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///
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/// For example, optimize icmp/fcmp brz/brnz sequences into ifcmp/ffcmp brif/brff
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/// sequences.
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fn optimize_cpu_flags(
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pos: &mut EncCursor,
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inst: Inst,
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last_flags_clobber: Option<Inst>,
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isa: &TargetIsa,
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) {
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// Look for compare and branch patterns.
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// This code could be considerably simplified with non-lexical lifetimes.
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let info = match pos.func.dfg[inst] {
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InstructionData::Branch {
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opcode,
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destination,
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ref args,
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} => {
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let first_arg = args.first(&pos.func.dfg.value_lists).unwrap();
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let invert_branch_cond = match opcode {
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Opcode::Brz => true,
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Opcode::Brnz => false,
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_ => panic!(),
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};
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if let ValueDef::Result(cond_inst, _) = pos.func.dfg.value_def(first_arg) {
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match pos.func.dfg[cond_inst] {
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InstructionData::IntCompare {
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cond,
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args: cmp_args,
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..
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} => CmpBrInfo {
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br_inst: inst,
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cmp_inst: cond_inst,
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destination,
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args: args.clone(),
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cmp_arg: cmp_args[0],
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invert_branch_cond,
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kind: CmpBrKind::Icmp {
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cond,
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arg: cmp_args[1],
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},
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},
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InstructionData::IntCompareImm {
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cond,
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arg: cmp_arg,
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imm: cmp_imm,
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..
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} => CmpBrInfo {
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br_inst: inst,
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cmp_inst: cond_inst,
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destination,
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args: args.clone(),
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cmp_arg,
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invert_branch_cond,
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kind: CmpBrKind::IcmpImm { cond, imm: cmp_imm },
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},
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InstructionData::FloatCompare {
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cond,
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args: cmp_args,
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..
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} => CmpBrInfo {
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br_inst: inst,
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cmp_inst: cond_inst,
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destination,
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args: args.clone(),
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cmp_arg: cmp_args[0],
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invert_branch_cond,
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kind: CmpBrKind::Fcmp {
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cond,
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arg: cmp_args[1],
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},
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},
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_ => return,
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}
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} else {
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return;
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}
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}
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// TODO: trapif, trueif, selectif, and their ff counterparts.
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_ => return,
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};
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// If any instructions clobber the flags between the comparison and the branch,
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// don't optimize them.
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if last_flags_clobber != Some(info.cmp_inst) {
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return;
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}
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// We found a compare+branch pattern. Transform it to use flags.
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let args = info.args.as_slice(&pos.func.dfg.value_lists)[1..].to_vec();
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pos.goto_inst(info.cmp_inst);
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match info.kind {
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CmpBrKind::Icmp { mut cond, arg } => {
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let flags = pos.ins().ifcmp(info.cmp_arg, arg);
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pos.func.dfg.replace(info.cmp_inst).trueif(cond, flags);
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if info.invert_branch_cond {
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cond = cond.inverse();
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}
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pos.func
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.dfg
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.replace(info.br_inst)
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.brif(cond, flags, info.destination, &args);
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}
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CmpBrKind::IcmpImm { mut cond, imm } => {
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let flags = pos.ins().ifcmp_imm(info.cmp_arg, imm);
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pos.func.dfg.replace(info.cmp_inst).trueif(cond, flags);
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if info.invert_branch_cond {
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cond = cond.inverse();
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}
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pos.func
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.dfg
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.replace(info.br_inst)
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.brif(cond, flags, info.destination, &args);
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}
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CmpBrKind::Fcmp { mut cond, arg } => {
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let flags = pos.ins().ffcmp(info.cmp_arg, arg);
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pos.func.dfg.replace(info.cmp_inst).trueff(cond, flags);
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if info.invert_branch_cond {
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cond = cond.inverse();
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}
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pos.func
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.dfg
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.replace(info.br_inst)
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.brff(cond, flags, info.destination, &args);
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}
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}
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let ok = pos.func.update_encoding(info.cmp_inst, isa).is_ok();
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debug_assert!(ok);
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let ok = pos.func.update_encoding(info.br_inst, isa).is_ok();
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debug_assert!(ok);
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}
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struct MemOpInfo {
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opcode: Opcode,
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itype: Type,
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arg: Value,
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st_arg: Option<Value>,
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flags: MemFlags,
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offset: Offset32,
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}
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fn optimize_complex_addresses(pos: &mut EncCursor, inst: Inst, isa: &TargetIsa) {
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// Look for simple loads and stores we can optimize.
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let info = match pos.func.dfg[inst] {
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InstructionData::Load {
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opcode,
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arg,
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flags,
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offset,
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} => MemOpInfo {
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opcode,
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itype: pos.func.dfg.ctrl_typevar(inst),
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arg,
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st_arg: None,
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flags,
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offset,
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},
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InstructionData::Store {
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opcode,
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args,
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flags,
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offset,
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} => MemOpInfo {
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opcode,
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itype: pos.func.dfg.ctrl_typevar(inst),
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arg: args[1],
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st_arg: Some(args[0]),
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flags,
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offset,
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},
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_ => return,
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};
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// Examine the instruction that defines the address operand.
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if let ValueDef::Result(result_inst, _) = pos.func.dfg.value_def(info.arg) {
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match pos.func.dfg[result_inst] {
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InstructionData::Binary {
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opcode: Opcode::Iadd,
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args,
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} => match info.opcode {
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// Operand is an iadd. Fold it into a memory address with a complex address mode.
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Opcode::Load => {
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pos.func.dfg.replace(inst).load_complex(
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info.itype,
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info.flags,
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&args,
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info.offset,
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);
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}
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Opcode::Uload8 => {
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pos.func.dfg.replace(inst).uload8_complex(
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info.itype,
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info.flags,
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&args,
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info.offset,
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);
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}
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Opcode::Sload8 => {
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pos.func.dfg.replace(inst).sload8_complex(
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info.itype,
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info.flags,
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&args,
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info.offset,
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);
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}
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Opcode::Uload16 => {
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pos.func.dfg.replace(inst).uload16_complex(
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info.itype,
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info.flags,
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&args,
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info.offset,
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);
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}
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Opcode::Sload16 => {
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pos.func.dfg.replace(inst).sload16_complex(
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info.itype,
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info.flags,
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&args,
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info.offset,
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);
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}
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Opcode::Uload32 => {
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pos.func
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.dfg
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.replace(inst)
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.uload32_complex(info.flags, &args, info.offset);
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}
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Opcode::Sload32 => {
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pos.func
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.dfg
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.replace(inst)
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.sload32_complex(info.flags, &args, info.offset);
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}
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Opcode::Store => {
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pos.func.dfg.replace(inst).store_complex(
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info.flags,
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info.st_arg.unwrap(),
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&args,
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info.offset,
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);
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}
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Opcode::Istore8 => {
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pos.func.dfg.replace(inst).istore8_complex(
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info.flags,
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info.st_arg.unwrap(),
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&args,
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info.offset,
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);
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}
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Opcode::Istore16 => {
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pos.func.dfg.replace(inst).istore16_complex(
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info.flags,
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info.st_arg.unwrap(),
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&args,
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info.offset,
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);
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}
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Opcode::Istore32 => {
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pos.func.dfg.replace(inst).istore32_complex(
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info.flags,
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info.st_arg.unwrap(),
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&args,
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info.offset,
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);
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}
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_ => panic!("Unsupported load or store opcode"),
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},
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InstructionData::BinaryImm {
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opcode: Opcode::IaddImm,
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arg,
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imm,
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} => match pos.func.dfg[inst] {
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// Operand is an iadd_imm. Fold the immediate into the offset if possible.
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InstructionData::Load {
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arg: ref mut load_arg,
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ref mut offset,
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..
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} => {
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if let Some(imm) = offset.try_add_i64(imm.into()) {
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*load_arg = arg;
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*offset = imm;
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} else {
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// Overflow.
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return;
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}
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}
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InstructionData::Store {
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args: ref mut store_args,
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ref mut offset,
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..
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} => {
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if let Some(imm) = offset.try_add_i64(imm.into()) {
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store_args[1] = arg;
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*offset = imm;
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} else {
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// Overflow.
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return;
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}
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}
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_ => panic!(),
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},
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_ => {
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// Address value is defined by some other kind of instruction.
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return;
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}
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}
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} else {
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// Address value is not the result of an instruction.
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return;
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}
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let ok = pos.func.update_encoding(inst, isa).is_ok();
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debug_assert!(ok);
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}
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//----------------------------------------------------------------------
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//
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// The main post-opt pass.
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pub fn do_postopt(func: &mut Function, isa: &TargetIsa) {
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let _tt = timing::postopt();
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let mut pos = EncCursor::new(func, isa);
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while let Some(_ebb) = pos.next_ebb() {
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let mut last_flags_clobber = None;
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while let Some(inst) = pos.next_inst() {
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if isa.uses_cpu_flags() {
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// Optimize instructions to make use of flags.
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optimize_cpu_flags(&mut pos, inst, last_flags_clobber, isa);
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// Track the most recent seen instruction that clobbers the flags.
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if let Some(constraints) = isa
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.encoding_info()
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.operand_constraints(pos.func.encodings[inst])
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{
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if constraints.clobbers_flags {
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last_flags_clobber = Some(inst)
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}
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}
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}
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if isa.uses_complex_addresses() {
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optimize_complex_addresses(&mut pos, inst, isa);
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}
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}
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}
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}
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