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moved crates in lib/ to src/, renamed crates, modified some files' text (#660)

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moved crates in lib/ to src/, renamed crates, modified some files' text (#660)
This commit is contained in:
lazypassion
2019-01-28 18:56:54 -05:00
committed by Dan Gohman
parent 54959cf5bb
commit 747ad3c4c5
508 changed files with 94 additions and 92 deletions
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33
cranelift/codegen/meta-python/isa/riscv/__init__.py Normal file
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"""
RISC-V Target
-------------
`RISC-V <https://riscv.org/>`_ is an open instruction set architecture
originally developed at UC Berkeley. It is a RISC-style ISA with either a
32-bit (RV32I) or 64-bit (RV32I) base instruction set and a number of optional
extensions:
RV32M / RV64M
Integer multiplication and division.
RV32A / RV64A
Atomics.
RV32F / RV64F
Single-precision IEEE floating point.
RV32D / RV64D
Double-precision IEEE floating point.
RV32G / RV64G
General purpose instruction sets. This represents the union of the I, M, A,
F, and D instruction sets listed above.
"""
from __future__ import absolute_import
from . import defs
from . import encodings, settings, registers # noqa
from cdsl.isa import TargetISA # noqa
# Re-export the primary target ISA definition.
ISA = defs.ISA.finish() # type: TargetISA

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cranelift/codegen/meta-python/isa/riscv/defs.py Normal file
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"""
RISC-V definitions.
Commonly used definitions.
"""
from __future__ import absolute_import
from cdsl.isa import TargetISA, CPUMode
import base.instructions
ISA = TargetISA('riscv', [base.instructions.GROUP]) # type: TargetISA
# CPU modes for 32-bit and 64-bit operation.
RV32 = CPUMode('RV32', ISA)
RV64 = CPUMode('RV64', ISA)

162
cranelift/codegen/meta-python/isa/riscv/encodings.py Normal file
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"""
RISC-V Encodings.
"""
from __future__ import absolute_import
from base import instructions as base
from base.immediates import intcc
from .defs import RV32, RV64
from .recipes import OPIMM, OPIMM32, OP, OP32, LUI, BRANCH, JALR, JAL
from .recipes import LOAD, STORE
from .recipes import R, Rshamt, Ricmp, Ii, Iz, Iicmp, Iret, Icall, Icopy
from .recipes import U, UJ, UJcall, SB, SBzero, GPsp, GPfi, Irmov
from .settings import use_m
from cdsl.ast import Var
from base.legalize import narrow, expand
RV32.legalize_monomorphic(expand)
RV32.legalize_type(
default=narrow,
i32=expand,
f32=expand,
f64=expand)
RV64.legalize_monomorphic(expand)
RV64.legalize_type(
default=narrow,
i32=expand,
i64=expand,
f32=expand,
f64=expand)
# Dummies for instruction predicates.
x = Var('x')
y = Var('y')
dest = Var('dest')
args = Var('args')
# Basic arithmetic binary instructions are encoded in an R-type instruction.
for inst, inst_imm, f3, f7 in [
(base.iadd, base.iadd_imm, 0b000, 0b0000000),
(base.isub, None, 0b000, 0b0100000),
(base.bxor, base.bxor_imm, 0b100, 0b0000000),
(base.bor, base.bor_imm, 0b110, 0b0000000),
(base.band, base.band_imm, 0b111, 0b0000000)
]:
RV32.enc(inst.i32, R, OP(f3, f7))
RV64.enc(inst.i64, R, OP(f3, f7))
# Immediate versions for add/xor/or/and.
if inst_imm:
RV32.enc(inst_imm.i32, Ii, OPIMM(f3))
RV64.enc(inst_imm.i64, Ii, OPIMM(f3))
# 32-bit ops in RV64.
RV64.enc(base.iadd.i32, R, OP32(0b000, 0b0000000))
RV64.enc(base.isub.i32, R, OP32(0b000, 0b0100000))
# There are no andiw/oriw/xoriw variations.
RV64.enc(base.iadd_imm.i32, Ii, OPIMM32(0b000))
# Use iadd_imm with %x0 to materialize constants.
RV32.enc(base.iconst.i32, Iz, OPIMM(0b000))
RV64.enc(base.iconst.i32, Iz, OPIMM(0b000))
RV64.enc(base.iconst.i64, Iz, OPIMM(0b000))
# Dynamic shifts have the same masking semantics as the clif base instructions.
for inst, inst_imm, f3, f7 in [
(base.ishl, base.ishl_imm, 0b001, 0b0000000),
(base.ushr, base.ushr_imm, 0b101, 0b0000000),
(base.sshr, base.sshr_imm, 0b101, 0b0100000),
]:
RV32.enc(inst.i32.i32, R, OP(f3, f7))
RV64.enc(inst.i64.i64, R, OP(f3, f7))
RV64.enc(inst.i32.i32, R, OP32(f3, f7))
# Allow i32 shift amounts in 64-bit shifts.
RV64.enc(inst.i64.i32, R, OP(f3, f7))
RV64.enc(inst.i32.i64, R, OP32(f3, f7))
# Immediate shifts.
RV32.enc(inst_imm.i32, Rshamt, OPIMM(f3, f7))
RV64.enc(inst_imm.i64, Rshamt, OPIMM(f3, f7))
RV64.enc(inst_imm.i32, Rshamt, OPIMM32(f3, f7))
# Signed and unsigned integer 'less than'. There are no 'w' variants for
# comparing 32-bit numbers in RV64.
RV32.enc(base.icmp.i32(intcc.slt, x, y), Ricmp, OP(0b010, 0b0000000))
RV64.enc(base.icmp.i64(intcc.slt, x, y), Ricmp, OP(0b010, 0b0000000))
RV32.enc(base.icmp.i32(intcc.ult, x, y), Ricmp, OP(0b011, 0b0000000))
RV64.enc(base.icmp.i64(intcc.ult, x, y), Ricmp, OP(0b011, 0b0000000))
RV32.enc(base.icmp_imm.i32(intcc.slt, x, y), Iicmp, OPIMM(0b010))
RV64.enc(base.icmp_imm.i64(intcc.slt, x, y), Iicmp, OPIMM(0b010))
RV32.enc(base.icmp_imm.i32(intcc.ult, x, y), Iicmp, OPIMM(0b011))
RV64.enc(base.icmp_imm.i64(intcc.ult, x, y), Iicmp, OPIMM(0b011))
# Integer constants with the low 12 bits clear are materialized by lui.
RV32.enc(base.iconst.i32, U, LUI())
RV64.enc(base.iconst.i32, U, LUI())
RV64.enc(base.iconst.i64, U, LUI())
# "M" Standard Extension for Integer Multiplication and Division.
# Gated by the `use_m` flag.
RV32.enc(base.imul.i32, R, OP(0b000, 0b0000001), isap=use_m)
RV64.enc(base.imul.i64, R, OP(0b000, 0b0000001), isap=use_m)
RV64.enc(base.imul.i32, R, OP32(0b000, 0b0000001), isap=use_m)
# Control flow.
# Unconditional branches.
RV32.enc(base.jump, UJ, JAL())
RV64.enc(base.jump, UJ, JAL())
RV32.enc(base.call, UJcall, JAL())
RV64.enc(base.call, UJcall, JAL())
# Conditional branches.
for cond, f3 in [
(intcc.eq, 0b000),
(intcc.ne, 0b001),
(intcc.slt, 0b100),
(intcc.sge, 0b101),
(intcc.ult, 0b110),
(intcc.uge, 0b111)
]:
RV32.enc(base.br_icmp.i32(cond, x, y, dest, args), SB, BRANCH(f3))
RV64.enc(base.br_icmp.i64(cond, x, y, dest, args), SB, BRANCH(f3))
for inst, f3 in [
(base.brz, 0b000),
(base.brnz, 0b001)
]:
RV32.enc(inst.i32, SBzero, BRANCH(f3))
RV64.enc(inst.i64, SBzero, BRANCH(f3))
RV32.enc(inst.b1, SBzero, BRANCH(f3))
RV64.enc(inst.b1, SBzero, BRANCH(f3))
# Returns are a special case of JALR using %x1 to hold the return address.
# The return address is provided by a special-purpose `link` return value that
# is added by legalize_signature().
RV32.enc(base.x_return, Iret, JALR())
RV64.enc(base.x_return, Iret, JALR())
RV32.enc(base.call_indirect.i32, Icall, JALR())
RV64.enc(base.call_indirect.i64, Icall, JALR())
# Spill and fill.
RV32.enc(base.spill.i32, GPsp, STORE(0b010))
RV64.enc(base.spill.i32, GPsp, STORE(0b010))
RV64.enc(base.spill.i64, GPsp, STORE(0b011))
RV32.enc(base.fill.i32, GPfi, LOAD(0b010))
RV64.enc(base.fill.i32, GPfi, LOAD(0b010))
RV64.enc(base.fill.i64, GPfi, LOAD(0b011))
# Register copies.
RV32.enc(base.copy.i32, Icopy, OPIMM(0b000))
RV64.enc(base.copy.i64, Icopy, OPIMM(0b000))
RV64.enc(base.copy.i32, Icopy, OPIMM32(0b000))
RV32.enc(base.regmove.i32, Irmov, OPIMM(0b000))
RV64.enc(base.regmove.i64, Irmov, OPIMM(0b000))
RV64.enc(base.regmove.i32, Irmov, OPIMM32(0b000))
RV32.enc(base.copy.b1, Icopy, OPIMM(0b000))
RV64.enc(base.copy.b1, Icopy, OPIMM(0b000))
RV32.enc(base.regmove.b1, Irmov, OPIMM(0b000))
RV64.enc(base.regmove.b1, Irmov, OPIMM(0b000))

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cranelift/codegen/meta-python/isa/riscv/recipes.py Normal file
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"""
RISC-V Encoding recipes.
The encoding recipes defined here more or less correspond to the RISC-V native
instruction formats described in the reference:
The RISC-V Instruction Set Manual
Volume I: User-Level ISA
Version 2.1
"""
from __future__ import absolute_import
from cdsl.isa import EncRecipe
from cdsl.predicates import IsSignedInt
from cdsl.registers import Stack
from base.formats import Binary, BinaryImm, MultiAry, IntCompare, IntCompareImm
from base.formats import Unary, UnaryImm, BranchIcmp, Branch, Jump
from base.formats import Call, CallIndirect, RegMove
from .registers import GPR
# The low 7 bits of a RISC-V instruction is the base opcode. All 32-bit
# instructions have 11 as the two low bits, with bits 6:2 determining the base
# opcode.
#
# Encbits for the 32-bit recipes are opcode[6:2] | (funct3 << 5) | ...
# The functions below encode the encbits.
def LOAD(funct3):
# type: (int) -> int
assert funct3 <= 0b111
return 0b00000 | (funct3 << 5)
def STORE(funct3):
# type: (int) -> int
assert funct3 <= 0b111
return 0b01000 | (funct3 << 5)
def BRANCH(funct3):
# type: (int) -> int
assert funct3 <= 0b111
return 0b11000 | (funct3 << 5)
def JALR(funct3=0):
# type: (int) -> int
assert funct3 <= 0b111
return 0b11001 | (funct3 << 5)
def JAL():
# type: () -> int
return 0b11011
def OPIMM(funct3, funct7=0):
# type: (int, int) -> int
assert funct3 <= 0b111
return 0b00100 | (funct3 << 5) | (funct7 << 8)
def OPIMM32(funct3, funct7=0):
# type: (int, int) -> int
assert funct3 <= 0b111
return 0b00110 | (funct3 << 5) | (funct7 << 8)
def OP(funct3, funct7):
# type: (int, int) -> int
assert funct3 <= 0b111
assert funct7 <= 0b1111111
return 0b01100 | (funct3 << 5) | (funct7 << 8)
def OP32(funct3, funct7):
# type: (int, int) -> int
assert funct3 <= 0b111
assert funct7 <= 0b1111111
return 0b01110 | (funct3 << 5) | (funct7 << 8)
def AIUPC():
# type: () -> int
return 0b00101
def LUI():
# type: () -> int
return 0b01101
# R-type 32-bit instructions: These are mostly binary arithmetic instructions.
# The encbits are `opcode[6:2] | (funct3 << 5) | (funct7 << 8)
R = EncRecipe(
'R', Binary, base_size=4, ins=(GPR, GPR), outs=GPR,
emit='put_r(bits, in_reg0, in_reg1, out_reg0, sink);')
# R-type with an immediate shift amount instead of rs2.
Rshamt = EncRecipe(
'Rshamt', BinaryImm, base_size=4, ins=GPR, outs=GPR,
emit='put_rshamt(bits, in_reg0, imm.into(), out_reg0, sink);')
# R-type encoding of an integer comparison.
Ricmp = EncRecipe(
'Ricmp', IntCompare, base_size=4, ins=(GPR, GPR), outs=GPR,
emit='put_r(bits, in_reg0, in_reg1, out_reg0, sink);')
Ii = EncRecipe(
'Ii', BinaryImm, base_size=4, ins=GPR, outs=GPR,
instp=IsSignedInt(BinaryImm.imm, 12),
emit='put_i(bits, in_reg0, imm.into(), out_reg0, sink);')
# I-type instruction with a hardcoded %x0 rs1.
Iz = EncRecipe(
'Iz', UnaryImm, base_size=4, ins=(), outs=GPR,
instp=IsSignedInt(UnaryImm.imm, 12),
emit='put_i(bits, 0, imm.into(), out_reg0, sink);')
# I-type encoding of an integer comparison.
Iicmp = EncRecipe(
'Iicmp', IntCompareImm, base_size=4, ins=GPR, outs=GPR,
instp=IsSignedInt(IntCompareImm.imm, 12),
emit='put_i(bits, in_reg0, imm.into(), out_reg0, sink);')
# I-type encoding for `jalr` as a return instruction. We won't use the
# immediate offset.
# The variable return values are not encoded.
Iret = EncRecipe(
'Iret', MultiAry, base_size=4, ins=(), outs=(),
emit='''
// Return instructions are always a jalr to %x1.
// The return address is provided as a special-purpose link argument.
put_i(
bits,
1, // rs1 = %x1
0, // no offset.
0, // rd = %x0: no address written.
sink,
);
''')
# I-type encoding for `jalr` as a call_indirect.
Icall = EncRecipe(
'Icall', CallIndirect, base_size=4, ins=GPR, outs=(),
emit='''
// call_indirect instructions are jalr with rd=%x1.
put_i(
bits,
in_reg0,
0, // no offset.
1, // rd = %x1: link register.
sink,
);
''')
# Copy of a GPR is implemented as addi x, 0.
Icopy = EncRecipe(
'Icopy', Unary, base_size=4, ins=GPR, outs=GPR,
emit='put_i(bits, in_reg0, 0, out_reg0, sink);')
# Same for a GPR regmove.
Irmov = EncRecipe(
'Irmov', RegMove, base_size=4, ins=GPR, outs=(),
emit='put_i(bits, src, 0, dst, sink);')
# U-type instructions have a 20-bit immediate that targets bits 12-31.
U = EncRecipe(
'U', UnaryImm, base_size=4, ins=(), outs=GPR,
instp=IsSignedInt(UnaryImm.imm, 32, 12),
emit='put_u(bits, imm.into(), out_reg0, sink);')
# UJ-type unconditional branch instructions.
UJ = EncRecipe(
'UJ', Jump, base_size=4, ins=(), outs=(), branch_range=(0, 21),
emit='''
let dest = i64::from(func.offsets[destination]);
let disp = dest - i64::from(sink.offset());
put_uj(bits, disp, 0, sink);
''')
UJcall = EncRecipe(
'UJcall', Call, base_size=4, ins=(), outs=(),
emit='''
sink.reloc_external(Reloc::RiscvCall,
&func.dfg.ext_funcs[func_ref].name,
0);
// rd=%x1 is the standard link register.
put_uj(bits, 0, 1, sink);
''')
# SB-type branch instructions.
SB = EncRecipe(
'SB', BranchIcmp, base_size=4,
ins=(GPR, GPR), outs=(),
branch_range=(0, 13),
emit='''
let dest = i64::from(func.offsets[destination]);
let disp = dest - i64::from(sink.offset());
put_sb(bits, disp, in_reg0, in_reg1, sink);
''')
# SB-type branch instruction with rs2 fixed to zero.
SBzero = EncRecipe(
'SBzero', Branch, base_size=4,
ins=(GPR), outs=(),
branch_range=(0, 13),
emit='''
let dest = i64::from(func.offsets[destination]);
let disp = dest - i64::from(sink.offset());
put_sb(bits, disp, in_reg0, 0, sink);
''')
# Spill of a GPR.
GPsp = EncRecipe(
'GPsp', Unary, base_size=4,
ins=GPR, outs=Stack(GPR),
emit='unimplemented!();')
# Fill of a GPR.
GPfi = EncRecipe(
'GPfi', Unary, base_size=4,
ins=Stack(GPR), outs=GPR,
emit='unimplemented!();')

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cranelift/codegen/meta-python/isa/riscv/registers.py Normal file
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"""
RISC-V register banks.
"""
from __future__ import absolute_import
from cdsl.registers import RegBank, RegClass
from .defs import ISA
# We include `x0`, a.k.a `zero` in the register bank. It will be reserved.
IntRegs = RegBank(
'IntRegs', ISA,
'General purpose registers',
units=32, prefix='x')
FloatRegs = RegBank(
'FloatRegs', ISA,
'Floating point registers',
units=32, prefix='f')
GPR = RegClass(IntRegs)
FPR = RegClass(FloatRegs)
RegClass.extract_names(globals())

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cranelift/codegen/meta-python/isa/riscv/settings.py Normal file
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"""
RISC-V settings.
"""
from __future__ import absolute_import
from cdsl.settings import SettingGroup, BoolSetting
from cdsl.predicates import And
import base.settings as shared
from .defs import ISA
ISA.settings = SettingGroup('riscv', parent=shared.group)
supports_m = BoolSetting("CPU supports the 'M' extension (mul/div)")
supports_a = BoolSetting("CPU supports the 'A' extension (atomics)")
supports_f = BoolSetting("CPU supports the 'F' extension (float)")
supports_d = BoolSetting("CPU supports the 'D' extension (double)")
enable_m = BoolSetting(
"Enable the use of 'M' instructions if available",
default=True)
enable_e = BoolSetting(
"Enable the 'RV32E' instruction set with only 16 registers")
use_m = And(supports_m, enable_m)
use_a = And(supports_a, shared.enable_atomics)
use_f = And(supports_f, shared.enable_float)
use_d = And(supports_d, shared.enable_float)
full_float = And(shared.enable_simd, supports_f, supports_d)
ISA.settings.close(globals())