T0b1/wasmtime
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Intel encodings for regspill and regfill.

Browse Source 
These are always SP-based.
This commit is contained in:
Jakob Stoklund Olesen
2017-10-04 17:01:40 -07:00
parent 826d4062fb
commit 73d4bb47c0
8 changed files with 138 additions and 55 deletions
Download Patch File Download Diff File Expand all files Collapse all files

10
cranelift/filetests/isa/intel/binary32-float.cton
View File

@@ -185,6 +185,11 @@ ebb0:
; asm: movd 1032(%esp), %xmm2
[-,%xmm2] v211 = fill v201 ; bin: 66 0f 6e 94 24 00000408
; asm: movd %xmm5, 1032(%rsp)
regspill v100, %xmm5 -> ss1 ; bin: 66 0f 7e ac 24 00000408
; asm: movd 1032(%rsp), %xmm5
regfill v100, ss1 -> %xmm5 ; bin: 66 0f 6e ac 24 00000408
; Comparisons.
;
; Only `supported_floatccs` are tested here. Others are handled by
@@ -388,6 +393,11 @@ ebb0:
; asm: movq 1032(%esp), %xmm2
[-,%xmm2] v211 = fill v201 ; bin: f3 0f 7e 94 24 00000408
; asm: movq %xmm5, 1032(%rsp)
regspill v100, %xmm5 -> ss1 ; bin: 66 0f d6 ac 24 00000408
; asm: movq 1032(%rsp), %xmm5
regfill v100, ss1 -> %xmm5 ; bin: f3 0f 7e ac 24 00000408
; Comparisons.
;
; Only `supported_floatccs` are tested here. Others are handled by

5
cranelift/filetests/isa/intel/binary32.cton
View File

@@ -363,6 +363,11 @@ ebb0:
; asm: movl 1032(%esp), %esi
[-,%rsi] v511 = fill v501 ; bin: 8b b4 24 00000408
; asm: movl %ecx, 1032(%esp)
regspill v1, %rcx -> ss1 ; bin: 89 8c 24 00000408
; asm: movl 1032(%esp), %ecx
regfill v1, ss1 -> %rcx ; bin: 8b 8c 24 00000408
; asm: testl %ecx, %ecx
; asm: je ebb1
brz v1, ebb1 ; bin: 85 c9 74 0e

10
cranelift/filetests/isa/intel/binary64-float.cton
View File

@@ -194,6 +194,11 @@ ebb0:
; asm: movd 1032(%rsp), %xmm10
[-,%xmm10] v211 = fill v201 ; bin: 66 44 0f 6e 94 24 00000408
; asm: movd %xmm5, 1032(%rsp)
regspill v100, %xmm5 -> ss1 ; bin: 66 0f 7e ac 24 00000408
; asm: movd 1032(%rsp), %xmm5
regfill v100, ss1 -> %xmm5 ; bin: 66 0f 6e ac 24 00000408
; Comparisons.
;
; Only `supported_floatccs` are tested here. Others are handled by
@@ -412,6 +417,11 @@ ebb0:
; asm: movq 1032(%rsp), %xmm10
[-,%xmm10] v211 = fill v201 ; bin: f3 44 0f 7e 94 24 00000408
; asm: movq %xmm5, 1032(%rsp)
regspill v100, %xmm5 -> ss1 ; bin: 66 0f d6 ac 24 00000408
; asm: movq 1032(%rsp), %xmm5
regfill v100, ss1 -> %xmm5 ; bin: f3 0f 7e ac 24 00000408
; Comparisons.
;
; Only `supported_floatccs` are tested here. Others are handled by

10
cranelift/filetests/isa/intel/binary64.cton
View File

@@ -459,6 +459,11 @@ ebb0:
; asm: movq 1032(%rsp), %r10
[-,%r10] v512 = fill v502 ; bin: 4c 8b 94 24 00000408
; asm: movq %rcx, 1032(%rsp)
regspill v1, %rcx -> ss1 ; bin: 48 89 8c 24 00000408
; asm: movq 1032(%rsp), %rcx
regfill v1, ss1 -> %rcx ; bin: 48 8b 8c 24 00000408
; asm: testq %rcx, %rcx
; asm: je ebb1
brz v1, ebb1 ; bin: 48 85 c9 74 1b
@@ -850,6 +855,11 @@ ebb0:
; asm: movl 1032(%rsp), %r10d
[-,%r10] v512 = fill v502 ; bin: 44 8b 94 24 00000408
; asm: movl %ecx, 1032(%rsp)
regspill v1, %rcx -> ss1 ; bin: 89 8c 24 00000408
; asm: movl 1032(%rsp), %ecx
regfill v1, ss1 -> %rcx ; bin: 8b 8c 24 00000408
; asm: testl %ecx, %ecx
; asm: je ebb1x
brz v1, ebb1 ; bin: 85 c9 74 18