Make legalization actions configurable.

When an instruction doesn't have a valid encoding for the target ISA, it
needs to be legalized. Different legalization strategies can be
expressed as separate XFormGroup objects.

Make the choice of XFormGroup configurable per CPU mode, rather than
depending on a hard-coded default.

Add a CPUMode.legalize_type() method which assigns an XFormGroup to
controlling type variables and lets you set a default.

Add a `legalize` field to Level1Entry so the first-level hash table
lookup gives us the configured default legalization action for the
instruction's controlling type variable.

lib/cretonne/meta/isa/arm32/defs.py

@@ -6,9 +6,14 @@ Commonly used definitions.
 from __future__ import absolute_import
 from cdsl.isa import TargetISA, CPUMode
 import base.instructions
+from base.legalize import narrow
 
 ISA = TargetISA('arm32', [base.instructions.GROUP])
 
 # CPU modes for 32-bit ARM and Thumb2.
 A32 = CPUMode('A32', ISA)
 T32 = CPUMode('T32', ISA)
+
+# TODO: Refine these.
+A32.legalize_type(narrow)
+T32.legalize_type(narrow)

lib/cretonne/meta/isa/arm64/defs.py

@@ -6,6 +6,10 @@ Commonly used definitions.
 from __future__ import absolute_import
 from cdsl.isa import TargetISA, CPUMode
 import base.instructions
+from base.legalize import narrow
 
 ISA = TargetISA('arm64', [base.instructions.GROUP])
 A64 = CPUMode('A64', ISA)
+
+# TODO: Refine these
+A64.legalize_type(narrow)

lib/cretonne/meta/isa/intel/encodings.py

@@ -9,6 +9,20 @@ from .defs import I32, I64
 from . import recipes as r
 from . import settings as cfg
 from . import instructions as x86
+from base.legalize import narrow, expand
+
+I32.legalize_type(
+        default=narrow,
+        i32=expand,
+        f32=expand,
+        f64=expand)
+
+I64.legalize_type(
+        default=narrow,
+        i32=expand,
+        i64=expand,
+        f32=expand,
+        f64=expand)
 
 for inst,           opc in [
         (base.iadd, 0x01),

lib/cretonne/meta/isa/riscv/encodings.py

@@ -11,6 +11,20 @@ from .recipes import R, Rshamt, Ricmp, I, Iz, Iicmp, Iret, Icall, Icopy
 from .recipes import U, UJ, UJcall, SB, SBzero, GPsp, GPfi, Irmov
 from .settings import use_m
 from cdsl.ast import Var
+from base.legalize import narrow, expand
+
+RV32.legalize_type(
+        default=narrow,
+        i32=expand,
+        f32=expand,
+        f64=expand)
+
+RV64.legalize_type(
+        default=narrow,
+        i32=expand,
+        i64=expand,
+        f32=expand,
+        f64=expand)
 
 # Dummies for instruction predicates.
 x = Var('x')