AArch64 SIMD: pattern-match load+splat into LD1R instruction.

cranelift/codegen/src/machinst/inst_common.rs

@@ -1,6 +1,8 @@
 //! A place to park MachInst::Inst fragments which are common across multiple architectures.
 
+use super::{LowerCtx, VCodeInst};
 use crate::ir::{self, Inst as IRInst};
+use smallvec::SmallVec;
 
 //============================================================================
 // Instruction input "slots".
@@ -22,6 +24,24 @@ pub(crate) struct InsnOutput {
     pub(crate) output: usize,
 }
 
+pub(crate) fn insn_inputs<I: VCodeInst, C: LowerCtx<I = I>>(
+    ctx: &C,
+    insn: IRInst,
+) -> SmallVec<[InsnInput; 4]> {
+    (0..ctx.num_inputs(insn))
+        .map(|i| InsnInput { insn, input: i })
+        .collect()
+}
+
+pub(crate) fn insn_outputs<I: VCodeInst, C: LowerCtx<I = I>>(
+    ctx: &C,
+    insn: IRInst,
+) -> SmallVec<[InsnOutput; 4]> {
+    (0..ctx.num_outputs(insn))
+        .map(|i| InsnOutput { insn, output: i })
+        .collect()
+}
+
 //============================================================================
 // Atomic instructions.