diff --git a/cranelift/codegen/meta/src/shared/instructions.rs b/cranelift/codegen/meta/src/shared/instructions.rs
index 2acecdbd75..a49b998914 100755
--- a/cranelift/codegen/meta/src/shared/instructions.rs
+++ b/cranelift/codegen/meta/src/shared/instructions.rs
@@ -3213,21 +3213,20 @@ pub(crate) fn define(
         .operands_out(vec![a]),
     );
 
-    let IntTo = &TypeVar::new(
-        "IntTo",
-        "A larger integer type with the same number of lanes",
-        TypeSetBuilder::new()
-            .ints(Interval::All)
-            .simd_lanes(Interval::All)
-            .build(),
-    );
-    let x = &Operand::new("x", Int);
-    let a = &Operand::new("a", IntTo);
+    {
+        let IntTo = &TypeVar::new(
+            "IntTo",
+            "A larger integer type with the same number of lanes",
+            TypeSetBuilder::new().ints(Interval::All).build(),
+        );
 
-    ig.push(
-        Inst::new(
-            "uextend",
-            r#"
+        let x = &Operand::new("x", Int);
+        let a = &Operand::new("a", IntTo);
+
+        ig.push(
+            Inst::new(
+                "uextend",
+                r#"
         Convert `x` to a larger integer type by zero-extending.
 
         Each lane in `x` is converted to a larger integer type by adding
@@ -3238,16 +3237,16 @@ pub(crate) fn define(
         and each lane must not have fewer bits that the input lanes. If the
         input and output types are the same, this is a no-op.
         "#,
-            &formats.unary,
-        )
-        .operands_in(vec![x])
-        .operands_out(vec![a]),
-    );
+                &formats.unary,
+            )
+            .operands_in(vec![x])
+            .operands_out(vec![a]),
+        );
 
-    ig.push(
-        Inst::new(
-            "sextend",
-            r#"
+        ig.push(
+            Inst::new(
+                "sextend",
+                r#"
         Convert `x` to a larger integer type by sign-extending.
 
         Each lane in `x` is converted to a larger integer type by replicating
@@ -3258,10 +3257,20 @@ pub(crate) fn define(
         and each lane must not have fewer bits that the input lanes. If the
         input and output types are the same, this is a no-op.
         "#,
-            &formats.unary,
-        )
-        .operands_in(vec![x])
-        .operands_out(vec![a]),
+                &formats.unary,
+            )
+            .operands_in(vec![x])
+            .operands_out(vec![a]),
+        );
+    }
+
+    let IntTo = &TypeVar::new(
+        "IntTo",
+        "A larger integer type with the same number of lanes",
+        TypeSetBuilder::new()
+            .ints(Interval::All)
+            .simd_lanes(Interval::All)
+            .build(),
     );
 
     let FloatTo = &TypeVar::new(
@@ -3272,6 +3281,7 @@ pub(crate) fn define(
             .simd_lanes(Interval::All)
             .build(),
     );
+
     let x = &Operand::new("x", Float);
     let a = &Operand::new("a", FloatTo);
 
diff --git a/cranelift/codegen/src/isa/s390x/lower.isle b/cranelift/codegen/src/isa/s390x/lower.isle
index 84e10b4fda..acbbf2082c 100644
--- a/cranelift/codegen/src/isa/s390x/lower.isle
+++ b/cranelift/codegen/src/isa/s390x/lower.isle
@@ -931,14 +931,14 @@
       (put_in_reg_zext64 x))
 
 ;; 128-bit target types.
-(rule (lower (has_type (vr128_ty ty) (uextend x @ (value_type $I8))))
-      (vec_insert_lane $I8X16 (vec_imm ty 0) x 15 (zero_reg)))
-(rule (lower (has_type (vr128_ty ty) (uextend x @ (value_type $I16))))
-      (vec_insert_lane $I16X8 (vec_imm ty 0) x 7 (zero_reg)))
-(rule (lower (has_type (vr128_ty ty) (uextend x @ (value_type $I32))))
-      (vec_insert_lane $I32X4 (vec_imm ty 0) x 3 (zero_reg)))
-(rule (lower (has_type (vr128_ty ty) (uextend x @ (value_type $I64))))
-      (vec_insert_lane $I64X2 (vec_imm ty 0) x 1 (zero_reg)))
+(rule (lower (has_type $I128 (uextend x @ (value_type $I8))))
+      (vec_insert_lane $I8X16 (vec_imm $I128 0) x 15 (zero_reg)))
+(rule (lower (has_type $I128 (uextend x @ (value_type $I16))))
+      (vec_insert_lane $I16X8 (vec_imm $I128 0) x 7 (zero_reg)))
+(rule (lower (has_type $I128 (uextend x @ (value_type $I32))))
+      (vec_insert_lane $I32X4 (vec_imm $I128 0) x 3 (zero_reg)))
+(rule (lower (has_type $I128 (uextend x @ (value_type $I64))))
+      (vec_insert_lane $I64X2 (vec_imm $I128 0) x 1 (zero_reg)))
 
 
 ;;;; Rules for `sextend` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
@@ -952,9 +952,9 @@
       (put_in_reg_sext64 x))
 
 ;; 128-bit target types.
-(rule (lower (has_type (vr128_ty ty) (sextend x)))
+(rule (lower (has_type $I128 (sextend x)))
       (let ((x_ext Reg (put_in_reg_sext64 x)))
-        (mov_to_vec128 ty (ashr_imm $I64 x_ext 63) x_ext)))
+        (mov_to_vec128 $I128 (ashr_imm $I64 x_ext 63) x_ext)))
 
 
 ;;;; Rules for `snarrow` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;