Adds support for legalizing CLZ, CTZ and POPCOUNT on baseline x86_64 targets.
Changes: * Adds a new generic instruction, SELECTIF, that does value selection (a la conditional move) similarly to existing SELECT, except that it is controlled by condition code input and flags-register inputs. * Adds a new Intel x86_64 variant, 'baseline', that supports SSE2 and nothing else. * Adds new Intel x86_64 instructions BSR and BSF. * Implements generic CLZ, CTZ and POPCOUNT on x86_64 'baseline' targets using the new BSR, BSF and SELECTIF instructions. * Implements SELECTIF on x86_64 targets using conditional-moves. * new test filetests/isa/intel/baseline_clz_ctz_popcount.cton (for legalization) * new test filetests/isa/intel/baseline_clz_ctz_popcount_encoding.cton (for encoding) * Allow lib/cretonne/meta/gen_legalizer.py to generate non-snake-caseified Rust without rustc complaining. Fixes #238.
This commit is contained in:
Julian Seward
committed by
Jakob Stoklund Olesen
Jakob Stoklund Olesen
parent
e3714ddd10
commit
6f8a54b6a5
@@ -700,6 +700,7 @@ Operations
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==========
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.. autoinst:: select
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.. autoinst:: selectif
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Constant materialization
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------------------------
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@@ -979,6 +980,10 @@ Instructions that can only be used by the Intel target ISA.
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.. autoinst:: isa.intel.instructions.cvtt2si
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.. autoinst:: isa.intel.instructions.fmin
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.. autoinst:: isa.intel.instructions.fmax
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.. autoinst:: isa.intel.instructions.bsf
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.. autoinst:: isa.intel.instructions.bsr
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.. autoinst:: isa.intel.instructions.push
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.. autoinst:: isa.intel.instructions.pop
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Instruction groups
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==================
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104
cranelift/filetests/isa/intel/baseline_clz_ctz_popcount.cton
Normal file
104
cranelift/filetests/isa/intel/baseline_clz_ctz_popcount.cton
Normal file
@@ -0,0 +1,104 @@
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test compile
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set is_64bit
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isa intel baseline
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; clz/ctz on 64 bit operands
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function %i64_clz(i64) -> i64 {
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ebb0(v10: i64):
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v11 = clz v10
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; check: x86_bsr
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; check: selectif.i64
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return v11
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}
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function %i64_ctz(i64) -> i64 {
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ebb1(v20: i64):
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v21 = ctz v20
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; check: x86_bsf
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; check: selectif.i64
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return v21
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}
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; clz/ctz on 32 bit operands
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function %i32_clz(i32) -> i32 {
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ebb0(v10: i32):
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v11 = clz v10
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; check: x86_bsr
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; check: selectif.i32
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return v11
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}
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function %i32_ctz(i32) -> i32 {
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ebb1(v20: i32):
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v21 = ctz v20
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; check: x86_bsf
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; check: selectif.i32
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return v21
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}
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; popcount on 64 bit operands
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function %i64_popcount(i64) -> i64 {
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ebb0(v30: i64):
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v31 = popcnt v30;
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; check: iconst.i32
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; check: ushr
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; check: iconst.i64
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; check: band
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; check: isub
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; check: iconst.i32
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; check: ushr
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; check: band
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; check: isub
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; check: iconst.i32
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; check: ushr
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; check: band
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; check: isub
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; check: iconst.i32
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; check: ushr
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; check: iadd
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; check: iconst.i64
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; check: band
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; check: iconst.i64
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; check: imul
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; check: iconst.i32
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; check: ushr
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return v31;
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}
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; popcount on 32 bit operands
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function %i32_popcount(i32) -> i32 {
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ebb0(v40: i32):
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v41 = popcnt v40;
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; check: iconst.i32
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; check: ushr
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; check: iconst.i32
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; check: band
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; check: isub
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; check: iconst.i32
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; check: ushr
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; check: band
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; check: isub
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; check: iconst.i32
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; check: ushr
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; check: band
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; check: isub
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; check: iconst.i32
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; check: ushr
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; check: iadd
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; check: iconst.i32
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; check: band
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; check: iconst.i32
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; check: imul
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; check: iconst.i32
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; check: ushr
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return v41;
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}
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@@ -0,0 +1,89 @@
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test binemit
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set is_64bit
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set is_compressed
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isa intel baseline
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; The binary encodings can be verified with the command:
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;
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; sed -ne 's/^ *; asm: *//p' filetests/isa/intel/baseline_clz_ctz_popcount_encoding.cton | llvm-mc -show-encoding -triple=x86_64
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;
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function %Foo() {
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ebb0:
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; 64-bit wide bsf
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[-,%r11] v10 = iconst.i64 0x1234
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; asm: bsfq %r11, %rcx
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[-,%rcx,%eflags] v11, v12 = x86_bsf v10 ; bin: 49 0f bc cb
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[-,%rdx] v14 = iconst.i64 0x5678
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; asm: bsfq %rdx, %r12
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[-,%r12,%eflags] v15, v16 = x86_bsf v14 ; bin: 4c 0f bc e2
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; asm: bsfq %rdx, %rdi
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[-,%rdi,%eflags] v17, v18 = x86_bsf v14 ; bin: 48 0f bc fa
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; 32-bit wide bsf
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[-,%r11] v20 = iconst.i32 0x1234
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; asm: bsfl %r11d, %ecx
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[-,%rcx,%eflags] v21, v22 = x86_bsf v20 ; bin: 41 0f bc cb
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[-,%rdx] v24 = iconst.i32 0x5678
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; asm: bsfl %edx, %r12d
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[-,%r12,%eflags] v25, v26 = x86_bsf v24 ; bin: 44 0f bc e2
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; asm: bsfl %edx, %esi
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[-,%rsi,%eflags] v27, v28 = x86_bsf v24 ; bin: 0f bc f2
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; 64-bit wide bsr
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[-,%r11] v30 = iconst.i64 0x1234
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; asm: bsrq %r11, %rcx
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[-,%rcx,%eflags] v31, v32 = x86_bsr v30 ; bin: 49 0f bd cb
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[-,%rdx] v34 = iconst.i64 0x5678
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; asm: bsrq %rdx, %r12
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[-,%r12,%eflags] v35, v36 = x86_bsr v34 ; bin: 4c 0f bd e2
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; asm: bsrq %rdx, %rdi
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[-,%rdi,%eflags] v37, v38 = x86_bsr v34 ; bin: 48 0f bd fa
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; 32-bit wide bsr
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[-,%r11] v40 = iconst.i32 0x1234
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; asm: bsrl %r11d, %ecx
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[-,%rcx,%eflags] v41, v42 = x86_bsr v40 ; bin: 41 0f bd cb
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[-,%rdx] v44 = iconst.i32 0x5678
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; asm: bsrl %edx, %r12d
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[-,%r12,%eflags] v45, v46 = x86_bsr v44 ; bin: 44 0f bd e2
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; asm: bsrl %edx, %esi
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[-,%rsi,%eflags] v47, v48 = x86_bsr v44 ; bin: 0f bd f2
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; 64-bit wide cmov
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; asm: cmoveq %r11, %rdx
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[-,%rdx] v51 = selectif.i64 eq v48, v30, v34 ; bin: 49 0f 44 d3
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; asm: cmoveq %rdi, %rdx
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[-,%rdx] v52 = selectif.i64 eq v48, v37, v34 ; bin: 48 0f 44 d7
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; 32-bit wide cmov
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; asm: cmovnel %r11d, %edx
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[-,%rdx] v60 = selectif.i32 ne v48, v40, v44 ; bin: 41 0f 45 d3
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; asm: cmovlel %esi, %edx
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[-,%rdx] v61 = selectif.i32 sle v48, v27, v44 ; bin: 0f 4e d6
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trap user0
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}
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@@ -42,7 +42,7 @@ ebb0:
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; nextln: $v3 = bxor v0, v2
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; nextln: }
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; Polymorphic istruction controlled by second operand.
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; Polymorphic instruction controlled by second operand.
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function %select() {
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ebb0(v90: i32, v91: i32, v92: b1):
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v0 = select v92, v90, v91
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@@ -52,6 +52,16 @@ ebb0(v90: i32, v91: i32, v92: b1):
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; nextln: $v0 = select $v92, $v90, $v91
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; nextln: }
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; Polymorphic instruction controlled by third operand.
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function %selectif() native {
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ebb0(v95: i32, v96: i32, v97: b1):
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v98 = selectif.i32 eq v97, v95, v96
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}
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; sameln: function %selectif() native {
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; nextln: ebb0(v0: i32, v1: i32, v2: b1):
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; nextln: v3 = selectif.i32 eq v2, v0, v1
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; nextln: }
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; Lane indexes.
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function %lanes() {
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ebb0:
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