x64: Add support for the pblendw instruction (#6023)

This commit adds another case for `shuffle` lowering to the x64 backend
for the `{,v}pblendw` instruction. This instruction selects 16-bit
values from either of the inputs corresponding to an immediate 8-bit-mask where
each bit selects the corresponding lane from the inputs.
This commit is contained in:
Alex Crichton
2023-03-15 12:20:43 -05:00
committed by GitHub
parent fcddb9ca81
commit 6ed90f86c8
8 changed files with 132 additions and 14 deletions

View File

@@ -1125,6 +1125,7 @@ pub enum SseOpcode {
Punpcklqdq,
Pshuflw,
Pshufhw,
Pblendw,
}
impl SseOpcode {
@@ -1318,7 +1319,8 @@ impl SseOpcode {
| SseOpcode::Roundps
| SseOpcode::Roundpd
| SseOpcode::Roundss
| SseOpcode::Roundsd => SSE41,
| SseOpcode::Roundsd
| SseOpcode::Pblendw => SSE41,
SseOpcode::Pcmpgtq => SSE42,
}
@@ -1521,6 +1523,7 @@ impl fmt::Debug for SseOpcode {
SseOpcode::Punpckhqdq => "punpckhqdq",
SseOpcode::Pshuflw => "pshuflw",
SseOpcode::Pshufhw => "pshufhw",
SseOpcode::Pblendw => "pblendw",
};
write!(fmt, "{}", name)
}
@@ -1705,7 +1708,8 @@ impl AvxOpcode {
| AvxOpcode::Vpextrb
| AvxOpcode::Vpextrw
| AvxOpcode::Vpextrd
| AvxOpcode::Vpextrq => {
| AvxOpcode::Vpextrq
| AvxOpcode::Vpblendw => {
smallvec![InstructionSet::AVX]
}
}

View File

@@ -2263,6 +2263,7 @@ pub(crate) fn emit(
AvxOpcode::Vpalignr => (false, LegacyPrefixes::_66, OpcodeMap::_0F3A, 0x0F),
AvxOpcode::Vinsertps => (false, LegacyPrefixes::_66, OpcodeMap::_0F3A, 0x21),
AvxOpcode::Vshufps => (false, LegacyPrefixes::None, OpcodeMap::_0F, 0xC6),
AvxOpcode::Vpblendw => (false, LegacyPrefixes::_66, OpcodeMap::_0F3A, 0x0E),
_ => panic!("unexpected rmr_imm_vex opcode {op:?}"),
};
@@ -2719,6 +2720,7 @@ pub(crate) fn emit(
SseOpcode::Pinsrw => (LegacyPrefixes::_66, 0x0FC4, 2),
SseOpcode::Pinsrd => (LegacyPrefixes::_66, 0x0F3A22, 3),
SseOpcode::Shufps => (LegacyPrefixes::None, 0x0FC6, 2),
SseOpcode::Pblendw => (LegacyPrefixes::_66, 0x0F3A0E, 3),
_ => unimplemented!("Opcode {:?} not implemented", op),
};
let rex = RexFlags::from(*size);