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x64: Improve memory support in {insert,extract}lane (#5982)

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* x64: Improve memory support in `{insert,extract}lane`

This commit improves adds support to Cranelift to emit `pextr{b,w,d,q}`
with a memory destination, merging a store-of-extract operation into one
instruction. Additionally AVX support is added for the `pextr*`
instructions.

I've additionally tried to ensure that codegen tests and runtests exist
for all forms of these instructions too.

* Add missing commas

* Fix tests
This commit is contained in:
Alex Crichton
2023-03-13 14:30:44 -05:00
committed by GitHub
parent 5c95e6fbaf
commit 6ecdc2482e
17 changed files with 1066 additions and 54 deletions
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30
cranelift/codegen/src/isa/x64/lower.isle
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@@ -2659,17 +2659,41 @@
;; f32 or f64 despite the source perhaps being an integer vector since the
;; result of the instruction is the same.
(rule 2 (lower (store flags
(has_type (ty_32 _) (extractlane value (u8_from_uimm8 0)))
(has_type $F32 (extractlane value (u8_from_uimm8 0)))
address
offset))
(side_effect
(x64_movss_store (to_amode flags address offset) value)))
(rule 3 (lower (store flags
(has_type (ty_64 _) (extractlane value (u8_from_uimm8 0)))
(rule 2 (lower (store flags
(has_type $F64 (extractlane value (u8_from_uimm8 0)))
address
offset))
(side_effect
(x64_movsd_store (to_amode flags address offset) value)))
(rule 2 (lower (store flags
(has_type $I8 (extractlane value (u8_from_uimm8 n)))
address
offset))
(side_effect
(x64_pextrb_store (to_amode flags address offset) value n)))
(rule 2 (lower (store flags
(has_type $I16 (extractlane value (u8_from_uimm8 n)))
address
offset))
(side_effect
(x64_pextrw_store (to_amode flags address offset) value n)))
(rule 2 (lower (store flags
(has_type $I32 (extractlane value (u8_from_uimm8 n)))
address
offset))
(side_effect
(x64_pextrd_store (to_amode flags address offset) value n)))
(rule 2 (lower (store flags
(has_type $I64 (extractlane value (u8_from_uimm8 n)))
address
offset))
(side_effect
(x64_pextrq_store (to_amode flags address offset) value n)))
;; Rules for `load*` + ALU op + `store*` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;