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Remove unused SourceLoc in many Mach data structures (#4180)

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* Remove unused srcloc in MachReloc

* Remove unused srcloc in MachTrap

* Use `into_iter` on array in bench code to suppress a warning

* Remove unused srcloc in MachCallSite
This commit is contained in:
Benjamin Bouvier
2022-05-23 18:27:28 +02:00
committed by GitHub
parent 32622b3e6f
commit 6e828df632
11 changed files with 82 additions and 222 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5
benches/instantiation.rs
View File

@@ -200,7 +200,7 @@ fn bench_instantiation(c: &mut Criterion) {
}
fn strategies() -> impl Iterator<Item = InstanceAllocationStrategy> {
std::array::IntoIter::new([
[
InstanceAllocationStrategy::OnDemand,
InstanceAllocationStrategy::Pooling {
strategy: Default::default(),
@@ -209,7 +209,8 @@ fn strategies() -> impl Iterator<Item = InstanceAllocationStrategy> {
..Default::default()
},
},
])
]
.into_iter()
}
criterion_group!(benches, bench_instantiation);

41
cranelift/codegen/src/isa/aarch64/inst/emit.rs
View File

@@ -964,7 +964,7 @@ impl MachInstEmit for Inst {
let srcloc = state.cur_srcloc();
if srcloc != SourceLoc::default() && !flags.notrap() {
// Register the offset at which the actual load instruction starts.
sink.add_trap(srcloc, TrapCode::HeapOutOfBounds);
sink.add_trap(TrapCode::HeapOutOfBounds);
}
match &mem {
@@ -1084,7 +1084,7 @@ impl MachInstEmit for Inst {
let srcloc = state.cur_srcloc();
if srcloc != SourceLoc::default() && !flags.notrap() {
// Register the offset at which the actual store instruction starts.
sink.add_trap(srcloc, TrapCode::HeapOutOfBounds);
sink.add_trap(TrapCode::HeapOutOfBounds);
}
match &mem {
@@ -1161,7 +1161,7 @@ impl MachInstEmit for Inst {
let srcloc = state.cur_srcloc();
if srcloc != SourceLoc::default() && !flags.notrap() {
// Register the offset at which the actual store instruction starts.
sink.add_trap(srcloc, TrapCode::HeapOutOfBounds);
sink.add_trap(TrapCode::HeapOutOfBounds);
}
match &mem {
&PairAMode::SignedOffset(reg, simm7) => {
@@ -1193,7 +1193,7 @@ impl MachInstEmit for Inst {
let srcloc = state.cur_srcloc();
if srcloc != SourceLoc::default() && !flags.notrap() {
// Register the offset at which the actual load instruction starts.
sink.add_trap(srcloc, TrapCode::HeapOutOfBounds);
sink.add_trap(TrapCode::HeapOutOfBounds);
}
match &mem {
@@ -1233,7 +1233,7 @@ impl MachInstEmit for Inst {
if srcloc != SourceLoc::default() && !flags.notrap() {
// Register the offset at which the actual load instruction starts.
sink.add_trap(srcloc, TrapCode::HeapOutOfBounds);
sink.add_trap(TrapCode::HeapOutOfBounds);
}
let opc = match self {
@@ -1279,7 +1279,7 @@ impl MachInstEmit for Inst {
if srcloc != SourceLoc::default() && !flags.notrap() {
// Register the offset at which the actual store instruction starts.
sink.add_trap(srcloc, TrapCode::HeapOutOfBounds);
sink.add_trap(TrapCode::HeapOutOfBounds);
}
let opc = match self {
@@ -1413,7 +1413,7 @@ impl MachInstEmit for Inst {
sink.bind_label(again_label);
let srcloc = state.cur_srcloc();
if srcloc != SourceLoc::default() {
sink.add_trap(srcloc, TrapCode::HeapOutOfBounds);
sink.add_trap(TrapCode::HeapOutOfBounds);
}
sink.put4(enc_ldaxr(ty, x27wr, x25)); // ldaxr x27, [x25]
let size = OperandSize::from_ty(ty);
@@ -1537,7 +1537,7 @@ impl MachInstEmit for Inst {
let srcloc = state.cur_srcloc();
if srcloc != SourceLoc::default() {
sink.add_trap(srcloc, TrapCode::HeapOutOfBounds);
sink.add_trap(TrapCode::HeapOutOfBounds);
}
if op == AtomicRMWLoopOp::Xchg {
sink.put4(enc_stlxr(ty, x24wr, x26, x25)); // stlxr w24, x26, [x25]
@@ -1599,7 +1599,7 @@ impl MachInstEmit for Inst {
sink.bind_label(again_label);
let srcloc = state.cur_srcloc();
if srcloc != SourceLoc::default() {
sink.add_trap(srcloc, TrapCode::HeapOutOfBounds);
sink.add_trap(TrapCode::HeapOutOfBounds);
}
// ldaxr x27, [x25]
sink.put4(enc_ldaxr(ty, x27wr, x25));
@@ -1626,7 +1626,7 @@ impl MachInstEmit for Inst {
let srcloc = state.cur_srcloc();
if srcloc != SourceLoc::default() {
sink.add_trap(srcloc, TrapCode::HeapOutOfBounds);
sink.add_trap(TrapCode::HeapOutOfBounds);
}
sink.put4(enc_stlxr(ty, x24wr, x28, x25)); // stlxr w24, x28, [x25]
@@ -2627,7 +2627,7 @@ impl MachInstEmit for Inst {
let srcloc = state.cur_srcloc();
if srcloc != SourceLoc::default() {
// Register the offset at which the actual load instruction starts.
sink.add_trap(srcloc, TrapCode::HeapOutOfBounds);
sink.add_trap(TrapCode::HeapOutOfBounds);
}
sink.put4(enc_ldst_vec(q, size, rn, rd));
@@ -2760,11 +2760,10 @@ impl MachInstEmit for Inst {
if let Some(s) = state.take_stack_map() {
sink.add_stack_map(StackMapExtent::UpcomingBytes(4), s);
}
let loc = state.cur_srcloc();
sink.add_reloc(loc, Reloc::Arm64Call, &info.dest, 0);
sink.add_reloc(Reloc::Arm64Call, &info.dest, 0);
sink.put4(enc_jump26(0b100101, 0));
if info.opcode.is_call() {
sink.add_call_site(loc, info.opcode);
sink.add_call_site(info.opcode);
}
}
&Inst::CallInd { ref info } => {
@@ -2773,9 +2772,8 @@ impl MachInstEmit for Inst {
}
let rn = allocs.next(info.rn);
sink.put4(0b1101011_0001_11111_000000_00000_00000 | (machreg_to_gpr(rn) << 5));
let loc = state.cur_srcloc();
if info.opcode.is_call() {
sink.add_call_site(loc, info.opcode);
sink.add_call_site(info.opcode);
}
}
&Inst::CondBr {
@@ -2830,8 +2828,7 @@ impl MachInstEmit for Inst {
sink.put4(0xd4200000);
}
&Inst::Udf { trap_code } => {
let srcloc = state.cur_srcloc();
sink.add_trap(srcloc, trap_code);
sink.add_trap(trap_code);
if let Some(s) = state.take_stack_map() {
sink.add_stack_map(StackMapExtent::UpcomingBytes(4), s);
}
@@ -2958,8 +2955,7 @@ impl MachInstEmit for Inst {
dest: BranchTarget::ResolvedOffset(12),
};
inst.emit(&[], sink, emit_info, state);
let srcloc = state.cur_srcloc();
sink.add_reloc(srcloc, Reloc::Abs8, name, offset);
sink.add_reloc(Reloc::Abs8, name, offset);
if emit_info.0.emit_all_ones_funcaddrs() {
sink.put8(u64::max_value());
} else {
@@ -3073,16 +3069,15 @@ impl MachInstEmit for Inst {
// See: https://gcc.godbolt.org/z/KhMh5Gvra
// adrp x0, <label>
sink.add_reloc(state.cur_srcloc(), Reloc::Aarch64TlsGdAdrPage21, symbol, 0);
sink.add_reloc(Reloc::Aarch64TlsGdAdrPage21, symbol, 0);
sink.put4(0x90000000);
// add x0, x0, <label>
sink.add_reloc(state.cur_srcloc(), Reloc::Aarch64TlsGdAddLo12Nc, symbol, 0);
sink.add_reloc(Reloc::Aarch64TlsGdAddLo12Nc, symbol, 0);
sink.put4(0x91000000);
// bl __tls_get_addr
sink.add_reloc(
state.cur_srcloc(),
Reloc::Arm64Call,
&ExternalName::LibCall(LibCall::ElfTlsGetAddr),
0,

61
cranelift/codegen/src/isa/s390x/inst/emit.rs
View File

@@ -133,7 +133,7 @@ pub fn mem_emit(
if add_trap && mem.can_trap() {
let srcloc = state.cur_srcloc();
if srcloc != SourceLoc::default() {
sink.add_trap(srcloc, TrapCode::HeapOutOfBounds);
sink.add_trap(TrapCode::HeapOutOfBounds);
}
}
@@ -162,12 +162,10 @@ pub fn mem_emit(
ref name, offset, ..
} => {
let reloc = Reloc::S390xPCRel32Dbl;
let srcloc = state.cur_srcloc();
put_with_reloc(
sink,
&enc_ril_b(opcode_ril.unwrap(), rd, 0),
2,
srcloc,
reloc,
name,
offset.into(),
@@ -203,7 +201,7 @@ pub fn mem_rs_emit(
if add_trap && mem.can_trap() {
let srcloc = state.cur_srcloc();
if srcloc != SourceLoc::default() {
sink.add_trap(srcloc, TrapCode::HeapOutOfBounds);
sink.add_trap(TrapCode::HeapOutOfBounds);
}
}
@@ -245,7 +243,7 @@ pub fn mem_imm8_emit(
if add_trap && mem.can_trap() {
let srcloc = state.cur_srcloc();
if srcloc != SourceLoc::default() {
sink.add_trap(srcloc, TrapCode::HeapOutOfBounds);
sink.add_trap(TrapCode::HeapOutOfBounds);
}
}
@@ -283,7 +281,7 @@ pub fn mem_imm16_emit(
if add_trap && mem.can_trap() {
let srcloc = state.cur_srcloc();
if srcloc != SourceLoc::default() {
sink.add_trap(srcloc, TrapCode::HeapOutOfBounds);
sink.add_trap(TrapCode::HeapOutOfBounds);
}
}
@@ -849,12 +847,12 @@ fn put(sink: &mut MachBuffer<Inst>, enc: &[u8]) {
}
/// Emit encoding to sink, adding a trap on the last byte.
fn put_with_trap(sink: &mut MachBuffer<Inst>, enc: &[u8], srcloc: SourceLoc, trap_code: TrapCode) {
fn put_with_trap(sink: &mut MachBuffer<Inst>, enc: &[u8], trap_code: TrapCode) {
let len = enc.len();
for i in 0..len - 1 {
sink.put1(enc[i]);
}
sink.add_trap(srcloc, trap_code);
sink.add_trap(trap_code);
sink.put1(enc[len - 1]);
}
@@ -863,7 +861,6 @@ fn put_with_reloc(
sink: &mut MachBuffer<Inst>,
enc: &[u8],
offset: usize,
ri2_srcloc: SourceLoc,
ri2_reloc: Reloc,
ri2_name: &ExternalName,
ri2_offset: i64,
@@ -872,7 +869,7 @@ fn put_with_reloc(
for i in 0..offset {
sink.put1(enc[i]);
}
sink.add_reloc(ri2_srcloc, ri2_reloc, ri2_name, ri2_offset + offset as i64);
sink.add_reloc(ri2_reloc, ri2_name, ri2_offset + offset as i64);
for i in offset..len {
sink.put1(enc[i]);
}
@@ -1204,33 +1201,29 @@ impl MachInstEmit for Inst {
let rn = allocs.next(rn);
let opcode = 0xb91d; // DSGFR
let srcloc = state.cur_srcloc();
let trap_code = TrapCode::IntegerDivisionByZero;
put_with_trap(sink, &enc_rre(opcode, gpr(0), rn), srcloc, trap_code);
put_with_trap(sink, &enc_rre(opcode, gpr(0), rn), trap_code);
}
&Inst::SDivMod64 { rn } => {
let rn = allocs.next(rn);
let opcode = 0xb90d; // DSGR
let srcloc = state.cur_srcloc();
let trap_code = TrapCode::IntegerDivisionByZero;
put_with_trap(sink, &enc_rre(opcode, gpr(0), rn), srcloc, trap_code);
put_with_trap(sink, &enc_rre(opcode, gpr(0), rn), trap_code);
}
&Inst::UDivMod32 { rn } => {
let rn = allocs.next(rn);
let opcode = 0xb997; // DLR
let srcloc = state.cur_srcloc();
let trap_code = TrapCode::IntegerDivisionByZero;
put_with_trap(sink, &enc_rre(opcode, gpr(0), rn), srcloc, trap_code);
put_with_trap(sink, &enc_rre(opcode, gpr(0), rn), trap_code);
}
&Inst::UDivMod64 { rn } => {
let rn = allocs.next(rn);
let opcode = 0xb987; // DLGR
let srcloc = state.cur_srcloc();
let trap_code = TrapCode::IntegerDivisionByZero;
put_with_trap(sink, &enc_rre(opcode, gpr(0), rn), srcloc, trap_code);
put_with_trap(sink, &enc_rre(opcode, gpr(0), rn), trap_code);
}
&Inst::Flogr { rn } => {
let rn = allocs.next(rn);
@@ -1491,11 +1484,9 @@ impl MachInstEmit for Inst {
CmpOp::CmpL64 => 0xb961, // CLGRT
_ => unreachable!(),
};
let srcloc = state.cur_srcloc();
put_with_trap(
sink,
&enc_rrf_cde(opcode, rn, rm, cond.bits(), 0),
srcloc,
trap_code,
);
}
@@ -1513,11 +1504,9 @@ impl MachInstEmit for Inst {
CmpOp::CmpS64 => 0xec70, // CGIT
_ => unreachable!(),
};
let srcloc = state.cur_srcloc();
put_with_trap(
sink,
&enc_rie_a(opcode, rn, imm as u16, cond.bits()),
srcloc,
trap_code,
);
}
@@ -1535,13 +1524,7 @@ impl MachInstEmit for Inst {
CmpOp::CmpL64 => 0xec71, // CLGIT
_ => unreachable!(),
};
let srcloc = state.cur_srcloc();
put_with_trap(
sink,
&enc_rie_a(opcode, rn, imm, cond.bits()),
srcloc,
trap_code,
);
put_with_trap(sink, &enc_rie_a(opcode, rn, imm, cond.bits()), trap_code);
}
&Inst::AtomicRmw {
@@ -1698,7 +1681,7 @@ impl MachInstEmit for Inst {
let srcloc = state.cur_srcloc();
if srcloc != SourceLoc::default() && mem.can_trap() {
sink.add_trap(srcloc, TrapCode::HeapOutOfBounds);
sink.add_trap(TrapCode::HeapOutOfBounds);
}
match &mem {
@@ -1781,7 +1764,7 @@ impl MachInstEmit for Inst {
let srcloc = state.cur_srcloc();
if srcloc != SourceLoc::default() && mem.can_trap() {
sink.add_trap(srcloc, TrapCode::HeapOutOfBounds);
sink.add_trap(TrapCode::HeapOutOfBounds);
}
match &mem {
@@ -1964,10 +1947,9 @@ impl MachInstEmit for Inst {
let rd = allocs.next_writable(rd);
let opcode = 0xa75; // BRAS
let srcloc = state.cur_srcloc();
let reg = writable_spilltmp_reg().to_reg();
put(sink, &enc_ri_b(opcode, reg, 12));
sink.add_reloc(srcloc, Reloc::Abs8, name, offset);
sink.add_reloc(Reloc::Abs8, name, offset);
if emit_info.flags.emit_all_ones_funcaddrs() {
sink.put8(u64::max_value());
} else {
@@ -2191,7 +2173,6 @@ impl MachInstEmit for Inst {
let opcode = 0xc05; // BRASL
let reloc = Reloc::S390xPCRel32Dbl;
let srcloc = state.cur_srcloc();
if let Some(s) = state.take_stack_map() {
sink.add_stack_map(StackMapExtent::UpcomingBytes(6), s);
}
@@ -2199,13 +2180,12 @@ impl MachInstEmit for Inst {
sink,
&enc_ril_b(opcode, link.to_reg(), 0),
2,
srcloc,
reloc,
&info.dest,
0,
);
if info.opcode.is_call() {
sink.add_call_site(srcloc, info.opcode);
sink.add_call_site(info.opcode);
}
}
&Inst::CallInd { link, ref info } => {
@@ -2213,13 +2193,12 @@ impl MachInstEmit for Inst {
let rn = allocs.next(info.rn);
let opcode = 0x0d; // BASR
let srcloc = state.cur_srcloc();
if let Some(s) = state.take_stack_map() {
sink.add_stack_map(StackMapExtent::UpcomingBytes(2), s);
}
put(sink, &enc_rr(opcode, link.to_reg(), rn));
if info.opcode.is_call() {
sink.add_call_site(srcloc, info.opcode);
sink.add_call_site(info.opcode);
}
}
&Inst::Ret { link, .. } => {
@@ -2282,8 +2261,7 @@ impl MachInstEmit for Inst {
if let Some(s) = state.take_stack_map() {
sink.add_stack_map(StackMapExtent::UpcomingBytes(2), s);
}
let srcloc = state.cur_srcloc();
put_with_trap(sink, &enc_e(0x0000), srcloc, trap_code);
put_with_trap(sink, &enc_e(0x0000), trap_code);
}
&Inst::TrapIf { cond, trap_code } => {
// Branch over trap if condition is false.
@@ -2293,8 +2271,7 @@ impl MachInstEmit for Inst {
if let Some(s) = state.take_stack_map() {
sink.add_stack_map(StackMapExtent::UpcomingBytes(2), s);
}
let srcloc = state.cur_srcloc();
put_with_trap(sink, &enc_e(0x0000), srcloc, trap_code);
put_with_trap(sink, &enc_e(0x0000), trap_code);
}
&Inst::JTSequence { ridx, ref targets } => {
let ridx = allocs.next(ridx);

12
cranelift/codegen/src/isa/x64/encoding/rex.rs
View File

@@ -13,7 +13,7 @@ use crate::{
ir::TrapCode,
isa::x64::inst::{
args::{Amode, OperandSize},
regs, EmitInfo, EmitState, Inst, LabelUse,
regs, EmitInfo, Inst, LabelUse,
},
machinst::MachBuffer,
};
@@ -276,7 +276,6 @@ impl Default for LegacyPrefixes {
/// indicate a 64-bit operation.
pub(crate) fn emit_std_enc_mem(
sink: &mut MachBuffer<Inst>,
state: &EmitState,
info: &EmitInfo,
prefixes: LegacyPrefixes,
opcodes: u32,
@@ -290,10 +289,9 @@ pub(crate) fn emit_std_enc_mem(
// 64-bit integer registers, because they are part of an address
// expression. But `enc_g` can be derived from a register of any class.
let srcloc = state.cur_srcloc();
let can_trap = mem_e.can_trap();
if can_trap {
sink.add_trap(srcloc, TrapCode::HeapOutOfBounds);
sink.add_trap(TrapCode::HeapOutOfBounds);
}
prefixes.emit(sink);
@@ -303,7 +301,7 @@ pub(crate) fn emit_std_enc_mem(
// If this is an access based off of RSP, it may trap with a stack overflow if it's the
// first touch of a new stack page.
if *base == regs::rsp() && !can_trap && info.flags.enable_probestack() {
sink.add_trap(srcloc, TrapCode::StackOverflow);
sink.add_trap(TrapCode::StackOverflow);
}
// First, the REX byte.
@@ -369,7 +367,7 @@ pub(crate) fn emit_std_enc_mem(
// If this is an access based off of RSP, it may trap with a stack overflow if it's the
// first touch of a new stack page.
if *reg_base == regs::rsp() && !can_trap && info.flags.enable_probestack() {
sink.add_trap(srcloc, TrapCode::StackOverflow);
sink.add_trap(TrapCode::StackOverflow);
}
let enc_base = int_reg_enc(*reg_base);
@@ -466,7 +464,6 @@ pub(crate) fn emit_std_enc_enc(
pub(crate) fn emit_std_reg_mem(
sink: &mut MachBuffer<Inst>,
state: &EmitState,
info: &EmitInfo,
prefixes: LegacyPrefixes,
opcodes: u32,
@@ -479,7 +476,6 @@ pub(crate) fn emit_std_reg_mem(
let enc_g = reg_enc(reg_g);
emit_std_enc_mem(
sink,
state,
info,
prefixes,
opcodes,

114
cranelift/codegen/src/isa/x64/inst/emit.rs
View File

@@ -45,15 +45,8 @@ fn one_way_jmp(sink: &mut MachBuffer<Inst>, cc: CC, label: MachLabel) {
}
/// Emits a relocation, attaching the current source location as well.
fn emit_reloc(
sink: &mut MachBuffer<Inst>,
state: &EmitState,
kind: Reloc,
name: &ExternalName,
addend: Addend,
) {
let srcloc = state.cur_srcloc();
sink.add_reloc(srcloc, kind, name, addend);
fn emit_reloc(sink: &mut MachBuffer<Inst>, kind: Reloc, name: &ExternalName, addend: Addend) {
sink.add_reloc(kind, name, addend);
}
/// The top-level emit function.
@@ -176,7 +169,6 @@ pub(crate) fn emit(
let amode = addr.finalize(state, sink);
emit_std_reg_mem(
sink,
state,
info,
LegacyPrefixes::None,
0x0FAF,
@@ -239,7 +231,6 @@ pub(crate) fn emit(
// Here we revert to the "normal" G-E ordering.
emit_std_reg_mem(
sink,
state,
info,
LegacyPrefixes::None,
opcode_m,
@@ -293,7 +284,6 @@ pub(crate) fn emit(
let enc_g = int_reg_enc(src2);
emit_std_enc_mem(
sink,
state,
info,
LegacyPrefixes::None,
opcode,
@@ -338,7 +328,6 @@ pub(crate) fn emit(
let amode = src.finalize(state, sink).with_allocs(allocs);
emit_std_reg_mem(
sink,
state,
info,
prefix,
opcode,
@@ -411,8 +400,7 @@ pub(crate) fn emit(
OperandSize::Size64 => (0xF7, LegacyPrefixes::None),
};
let loc = state.cur_srcloc();
sink.add_trap(loc, TrapCode::IntegerDivisionByZero);
sink.add_trap(TrapCode::IntegerDivisionByZero);
let subopcode = if *signed { 7 } else { 6 };
match divisor.clone().to_reg_mem() {
@@ -433,7 +421,6 @@ pub(crate) fn emit(
let amode = src.finalize(state, sink).with_allocs(allocs);
emit_std_enc_mem(
sink,
state,
info,
prefix,
opcode,
@@ -479,9 +466,7 @@ pub(crate) fn emit(
}
RegMem::Mem { addr: src } => {
let amode = src.finalize(state, sink).with_allocs(allocs);
emit_std_enc_mem(
sink, state, info, prefix, 0xF7, 1, subopcode, &amode, rex_flags, 0,
);
emit_std_enc_mem(sink, info, prefix, 0xF7, 1, subopcode, &amode, rex_flags, 0);
}
}
}
@@ -748,7 +733,6 @@ pub(crate) fn emit(
emit_std_reg_mem(
sink,
state,
info,
LegacyPrefixes::None,
opcodes,
@@ -768,7 +752,6 @@ pub(crate) fn emit(
emit_std_reg_mem(
sink,
state,
info,
LegacyPrefixes::None,
0x8B,
@@ -786,7 +769,6 @@ pub(crate) fn emit(
emit_std_reg_mem(
sink,
state,
info,
LegacyPrefixes::None,
0x8D,
@@ -849,7 +831,6 @@ pub(crate) fn emit(
emit_std_reg_mem(
sink,
state,
info,
LegacyPrefixes::None,
opcodes,
@@ -886,7 +867,7 @@ pub(crate) fn emit(
// 16-bit: MOV r16, r/m16 is 66 (REX.W==0) 89 /r
// 32-bit: MOV r32, r/m32 is (REX.W==0) 89 /r
// 64-bit: MOV r64, r/m64 is (REX.W==1) 89 /r
emit_std_reg_mem(sink, state, info, prefix, opcode, 1, src, dst, rex, 0);
emit_std_reg_mem(sink, info, prefix, opcode, 1, src, dst, rex, 0);
}
Inst::ShiftR {
@@ -996,18 +977,7 @@ pub(crate) fn emit(
}
RegMemImm::Mem { addr } => {
let addr = &addr.finalize(state, sink).with_allocs(allocs);
emit_std_reg_mem(
sink,
state,
info,
prefix,
opcode_bytes,
2,
dst,
addr,
rex,
0,
);
emit_std_reg_mem(sink, info, prefix, opcode_bytes, 2, dst, addr, rex, 0);
}
RegMemImm::Imm { .. } => unreachable!(),
}
@@ -1062,7 +1032,7 @@ pub(crate) fn emit(
(OperandSize::Size8, false) => 0x84,
(_, false) => 0x85,
};
emit_std_reg_mem(sink, state, info, prefix, opcode, 1, reg_g, addr, rex, 0);
emit_std_reg_mem(sink, info, prefix, opcode, 1, reg_g, addr, rex, 0);
}
RegMemImm::Imm { simm32 } => {
@@ -1136,9 +1106,7 @@ pub(crate) fn emit(
}
RegMem::Mem { addr } => {
let addr = &addr.finalize(state, sink).with_allocs(allocs);
emit_std_reg_mem(
sink, state, info, prefix, opcode, 2, dst, addr, rex_flags, 0,
);
emit_std_reg_mem(sink, info, prefix, opcode, 2, dst, addr, rex_flags, 0);
}
}
}
@@ -1177,7 +1145,7 @@ pub(crate) fn emit(
let src = src.clone().to_reg_mem_imm().with_allocs(allocs);
if info.flags.enable_probestack() {
sink.add_trap(state.cur_srcloc(), TrapCode::StackOverflow);
sink.add_trap(TrapCode::StackOverflow);
}
match src {
@@ -1194,7 +1162,6 @@ pub(crate) fn emit(
let addr = &addr.finalize(state, sink);
emit_std_enc_mem(
sink,
state,
info,
LegacyPrefixes::None,
0xFF,
@@ -1230,7 +1197,7 @@ pub(crate) fn emit(
Inst::CallKnown { dest, opcode, .. } => {
if info.flags.enable_probestack() {
sink.add_trap(state.cur_srcloc(), TrapCode::StackOverflow);
sink.add_trap(TrapCode::StackOverflow);
}
if let Some(s) = state.take_stack_map() {
sink.add_stack_map(StackMapExtent::UpcomingBytes(5), s);
@@ -1238,11 +1205,10 @@ pub(crate) fn emit(
sink.put1(0xE8);
// The addend adjusts for the difference between the end of the instruction and the
// beginning of the immediate field.
emit_reloc(sink, state, Reloc::X86CallPCRel4, &dest, -4);
emit_reloc(sink, Reloc::X86CallPCRel4, &dest, -4);
sink.put4(0);
if opcode.is_call() {
let loc = state.cur_srcloc();
sink.add_call_site(loc, *opcode);
sink.add_call_site(*opcode);
}
}
@@ -1250,7 +1216,7 @@ pub(crate) fn emit(
let dest = dest.with_allocs(allocs);
if info.flags.enable_probestack() {
sink.add_trap(state.cur_srcloc(), TrapCode::StackOverflow);
sink.add_trap(TrapCode::StackOverflow);
}
let start_offset = sink.cur_offset();
match dest {
@@ -1271,7 +1237,6 @@ pub(crate) fn emit(
let addr = &addr.finalize(state, sink);
emit_std_enc_mem(
sink,
state,
info,
LegacyPrefixes::None,
0xFF,
@@ -1287,8 +1252,7 @@ pub(crate) fn emit(
sink.add_stack_map(StackMapExtent::StartedAtOffset(start_offset), s);
}
if opcode.is_call() {
let loc = state.cur_srcloc();
sink.add_call_site(loc, *opcode);
sink.add_call_site(*opcode);
}
}
@@ -1373,7 +1337,6 @@ pub(crate) fn emit(
let addr = &addr.finalize(state, sink);
emit_std_enc_mem(
sink,
state,
info,
LegacyPrefixes::None,
0xFF,
@@ -1548,18 +1511,7 @@ pub(crate) fn emit(
}
RegMem::Mem { addr } => {
let addr = &addr.finalize(state, sink);
emit_std_reg_mem(
sink,
state,
info,
prefix,
opcode,
num_opcodes,
reg_g,
addr,
rex,
0,
);
emit_std_reg_mem(sink, info, prefix, opcode, num_opcodes, reg_g, addr, rex, 0);
}
};
}
@@ -1717,9 +1669,7 @@ pub(crate) fn emit(
}
RegMem::Mem { addr } => {
let addr = &addr.finalize(state, sink);
emit_std_reg_mem(
sink, state, info, prefix, opcode, length, reg_g, addr, rex, 0,
);
emit_std_reg_mem(sink, info, prefix, opcode, length, reg_g, addr, rex, 0);
}
}
}
@@ -1916,7 +1866,7 @@ pub(crate) fn emit(
"No existing way to encode a mem argument in the ModRM r/m field."
);
// N.B.: bytes_at_end == 1, because of the `imm` byte below.
emit_std_reg_mem(sink, state, info, prefix, opcode, len, dst, addr, rex, 1);
emit_std_reg_mem(sink, info, prefix, opcode, len, dst, addr, rex, 1);
}
}
sink.put1(*imm);
@@ -1951,7 +1901,6 @@ pub(crate) fn emit(
let dst = &dst.finalize(state, sink);
emit_std_reg_mem(
sink,
state,
info,
prefix,
opcode,
@@ -2013,7 +1962,7 @@ pub(crate) fn emit(
}
RegMem::Mem { addr } => {
let addr = &addr.finalize(state, sink);
emit_std_reg_mem(sink, state, info, prefix, opcode, 2, reg_g, addr, rex, 0);
emit_std_reg_mem(sink, info, prefix, opcode, 2, reg_g, addr, rex, 0);
}
}
}
@@ -2036,7 +1985,7 @@ pub(crate) fn emit(
}
RegMem::Mem { addr } => {
let addr = &addr.finalize(state, sink);
emit_std_reg_mem(sink, state, info, prefix, opcode, len, dst, addr, rex, 0);
emit_std_reg_mem(sink, info, prefix, opcode, len, dst, addr, rex, 0);
}
}
}
@@ -2585,7 +2534,7 @@ pub(crate) fn emit(
sink.put1(0x48 | ((enc_dst >> 3) & 1) << 2);
sink.put1(0x8B);
sink.put1(0x05 | ((enc_dst & 7) << 3));
emit_reloc(sink, state, Reloc::X86GOTPCRel4, name, -4);
emit_reloc(sink, Reloc::X86GOTPCRel4, name, -4);
sink.put4(0);
// Offset in the relocation above applies to the address of the *GOT entry*, not
// the loaded address; so we emit a separate add or sub instruction if needed.
@@ -2608,7 +2557,7 @@ pub(crate) fn emit(
let enc_dst = int_reg_enc(dst);
sink.put1(0x48 | ((enc_dst >> 3) & 1));
sink.put1(0xB8 | (enc_dst & 7));
emit_reloc(sink, state, Reloc::Abs8, name, *offset);
emit_reloc(sink, Reloc::Abs8, name, *offset);
if info.flags.emit_all_ones_funcaddrs() {
sink.put8(u64::max_value());
} else {
@@ -2643,18 +2592,7 @@ pub(crate) fn emit(
};
let rex = RexFlags::from((OperandSize::from_ty(*ty), replacement));
let amode = mem.finalize(state, sink);
emit_std_reg_mem(
sink,
state,
info,
prefix,
opcodes,
2,
replacement,
&amode,
rex,
0,
);
emit_std_reg_mem(sink, info, prefix, opcodes, 2, replacement, &amode, rex, 0);
}
Inst::AtomicRmwSeq {
@@ -2794,8 +2732,7 @@ pub(crate) fn emit(
}
Inst::Ud2 { trap_code } => {
let cur_srcloc = state.cur_srcloc();
sink.add_trap(cur_srcloc, *trap_code);
sink.add_trap(*trap_code);
if let Some(s) = state.take_stack_map() {
sink.add_stack_map(StackMapExtent::UpcomingBytes(2), s);
}
@@ -2908,7 +2845,7 @@ pub(crate) fn emit(
sink.put1(0b01001000); // REX.W
sink.put1(0x8d); // LEA
sink.put1(0x3d); // ModRM byte
emit_reloc(sink, state, Reloc::ElfX86_64TlsGd, symbol, -4);
emit_reloc(sink, Reloc::ElfX86_64TlsGd, symbol, -4);
sink.put4(0); // offset
// data16 data16 callq __tls_get_addr-4
@@ -2918,7 +2855,6 @@ pub(crate) fn emit(
sink.put1(0xe8); // CALL
emit_reloc(
sink,
state,
Reloc::X86CallPLTRel4,
&ExternalName::LibCall(LibCall::ElfTlsGetAddr),
-4,
@@ -2931,7 +2867,7 @@ pub(crate) fn emit(
sink.put1(0x48); // REX.w
sink.put1(0x8b); // MOV
sink.put1(0x3d); // ModRM byte
emit_reloc(sink, state, Reloc::MachOX86_64Tlv, symbol, -4);
emit_reloc(sink, Reloc::MachOX86_64Tlv, symbol, -4);
sink.put4(0); // offset
// callq *(%rdi)

8
cranelift/codegen/src/isa/x64/inst/mod.rs
View File

@@ -601,9 +601,7 @@ impl Inst {
}
pub(crate) fn trap(trap_code: TrapCode) -> Inst {
Inst::Ud2 {
trap_code: trap_code,
}
Inst::Ud2 { trap_code }
}
pub(crate) fn setcc(cc: CC, dst: Writable<Reg>) -> Inst {
@@ -2432,10 +2430,6 @@ impl EmitState {
fn clear_post_insn(&mut self) {
self.stack_map = None;
}
pub(crate) fn cur_srcloc(&self) -> SourceLoc {
self.cur_srcloc
}
}
/// A label-use (internal relocation) in generated code.

43
cranelift/codegen/src/machinst/buffer.rs
View File

@@ -1231,13 +1231,7 @@ impl<I: VCodeInst> MachBuffer<I> {
}
/// Add an external relocation at the current offset.
pub fn add_reloc(
&mut self,
srcloc: SourceLoc,
kind: Reloc,
name: &ExternalName,
addend: Addend,
) {
pub fn add_reloc(&mut self, kind: Reloc, name: &ExternalName, addend: Addend) {
let name = name.clone();
// FIXME(#3277): This should use `I::LabelUse::from_reloc` to optionally
// generate a label-use statement to track whether an island is possibly
@@ -1274,7 +1268,6 @@ impl<I: VCodeInst> MachBuffer<I> {
// actually result in any memory unsafety or anything like that.
self.relocs.push(MachReloc {
offset: self.data.len() as CodeOffset,
srcloc,
kind,
name,
addend,
@@ -1282,23 +1275,21 @@ impl<I: VCodeInst> MachBuffer<I> {
}
/// Add a trap record at the current offset.
pub fn add_trap(&mut self, srcloc: SourceLoc, code: TrapCode) {
pub fn add_trap(&mut self, code: TrapCode) {
self.traps.push(MachTrap {
offset: self.data.len() as CodeOffset,
srcloc,
code,
});
}
/// Add a call-site record at the current offset.
pub fn add_call_site(&mut self, srcloc: SourceLoc, opcode: Opcode) {
pub fn add_call_site(&mut self, opcode: Opcode) {
debug_assert!(
opcode.is_call(),
"adding call site info for a non-call instruction."
);
self.call_sites.push(MachCallSite {
ret_addr: self.data.len() as CodeOffset,
srcloc,
opcode,
});
}
@@ -1446,8 +1437,6 @@ pub struct MachReloc {
/// The offset at which the relocation applies, *relative to the
/// containing section*.
pub offset: CodeOffset,
/// The original source location.
pub srcloc: SourceLoc,
/// The kind of relocation.
pub kind: Reloc,
/// The external symbol / name to which this relocation refers.
@@ -1462,8 +1451,6 @@ pub struct MachTrap {
/// The offset at which the trap instruction occurs, *relative to the
/// containing section*.
pub offset: CodeOffset,
/// The original source location.
pub srcloc: SourceLoc,
/// The trap code.
pub code: TrapCode,
}
@@ -1473,8 +1460,6 @@ pub struct MachTrap {
pub struct MachCallSite {
/// The offset of the call's return address, *relative to the containing section*.
pub ret_addr: CodeOffset,
/// The original source location.
pub srcloc: SourceLoc,
/// The call's opcode.
pub opcode: Opcode,
}
@@ -1987,24 +1972,14 @@ mod test {
buf.bind_label(label(0));
buf.put1(1);
buf.add_trap(SourceLoc::default(), TrapCode::HeapOutOfBounds);
buf.add_trap(TrapCode::HeapOutOfBounds);
buf.put1(2);
buf.add_trap(SourceLoc::default(), TrapCode::IntegerOverflow);
buf.add_trap(SourceLoc::default(), TrapCode::IntegerDivisionByZero);
buf.add_call_site(SourceLoc::default(), Opcode::Call);
buf.add_reloc(
SourceLoc::default(),
Reloc::Abs4,
&ExternalName::user(0, 0),
0,
);
buf.add_trap(TrapCode::IntegerOverflow);
buf.add_trap(TrapCode::IntegerDivisionByZero);
buf.add_call_site(Opcode::Call);
buf.add_reloc(Reloc::Abs4, &ExternalName::user(0, 0), 0);
buf.put1(3);
buf.add_reloc(
SourceLoc::default(),
Reloc::Abs8,
&ExternalName::user(1, 1),
1,
);
buf.add_reloc(Reloc::Abs8, &ExternalName::user(1, 1), 1);
buf.put1(4);
let buf = buf.finish();

1
cranelift/jit/src/compiled_blob.rs
View File

@@ -22,7 +22,6 @@ impl CompiledBlob {
for &MachReloc {
kind,
offset,
srcloc: _,
ref name,
addend,
} in &self.relocs

4
cranelift/module/src/data_context.rs
View File

@@ -2,7 +2,7 @@
use cranelift_codegen::binemit::{Addend, CodeOffset, Reloc};
use cranelift_codegen::entity::PrimaryMap;
use cranelift_codegen::ir::{self, SourceLoc};
use cranelift_codegen::ir;
use cranelift_codegen::MachReloc;
use std::borrow::ToOwned;
use std::boxed::Box;
@@ -66,7 +66,6 @@ impl DataDescription {
.map(move |&(offset, id)| MachReloc {
kind: pointer_reloc,
offset,
srcloc: SourceLoc::default(),
name: self.function_decls[id].clone(),
addend: 0,
});
@@ -76,7 +75,6 @@ impl DataDescription {
.map(move |&(offset, id, addend)| MachReloc {
kind: pointer_reloc,
offset,
srcloc: SourceLoc::default(),
name: self.data_decls[id].clone(),
addend,
});

8
cranelift/src/disasm.rs
View File

@@ -9,7 +9,6 @@ pub fn print_relocs(relocs: &[MachReloc]) -> String {
for &MachReloc {
kind,
offset,
srcloc: _,
ref name,
addend,
} in relocs
@@ -26,12 +25,7 @@ pub fn print_relocs(relocs: &[MachReloc]) -> String {
pub fn print_traps(traps: &[MachTrap]) -> String {
let mut text = String::new();
for &MachTrap {
offset,
srcloc: _,
code,
} in traps
{
for &MachTrap { offset, code } in traps {
writeln!(text, "trap: {} at {}", code, offset).unwrap();
}
text

7
crates/cranelift/src/compiler.rs
View File

@@ -657,7 +657,6 @@ fn collect_address_maps(
fn mach_reloc_to_reloc(reloc: &MachReloc) -> Relocation {
let &MachReloc {
offset,
srcloc: _,
kind,
ref name,
addend,
@@ -679,11 +678,7 @@ fn mach_reloc_to_reloc(reloc: &MachReloc) -> Relocation {
}
fn mach_trap_to_trap(trap: &MachTrap) -> TrapInformation {
let &MachTrap {
offset,
srcloc: _,
code,
} = trap;
let &MachTrap { offset, code } = trap;
TrapInformation {
code_offset: offset,
trap_code: match code {