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Fix 128-bit left shift: null out tmp3, not tmp2, on zero-shift case.

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Add a bunch of test vectors that actually expose this (previously the
shift-by-zero test had equal lower and upper halves and hid the bug),
including the most basic of all, 1 << 0 == 1 (thanks @bjorn3 for finding
this).
This commit is contained in:
Chris Fallin
2021-02-25 09:08:28 -08:00
parent 0f3e00b25e
commit 6dcb31abb7
2 changed files with 16 additions and 6 deletions
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4
cranelift/codegen/src/isa/x64/lower.rs
View File

@@ -888,7 +888,7 @@ fn emit_shl_i128<C: LowerCtx<I = Inst>>(
// shr tmp3, amt // shr tmp3, amt
// xor dst_lo, dst_lo // xor dst_lo, dst_lo
// test amt_src, 127 // test amt_src, 127
// cmovz tmp2, dst_lo // cmovz tmp3, dst_lo
// or tmp3, tmp2 // or tmp3, tmp2
// mov amt, amt_src // mov amt, amt_src
// and amt, 64 // and amt, 64
@@ -963,7 +963,7 @@ fn emit_shl_i128<C: LowerCtx<I = Inst>>(
OperandSize::Size64, OperandSize::Size64,
CC::Z, CC::Z,
RegMem::reg(dst_lo.to_reg()), RegMem::reg(dst_lo.to_reg()),
tmp2, tmp3,
)); ));
ctx.emit(Inst::alu_rmi_r( ctx.emit(Inst::alu_rmi_r(

18
cranelift/filetests/filetests/isa/x64/shift-i128-run.clif
View File

@@ -14,6 +14,11 @@ block0(v0: i64, v1: i64, v2: i8):
; run: %ishl(0x01010101_01010101, 0xffffffff_ffffffff, 66) == [0x00000000_00000000, 0x04040404_04040404] ; run: %ishl(0x01010101_01010101, 0xffffffff_ffffffff, 66) == [0x00000000_00000000, 0x04040404_04040404]
; run: %ishl(0x01010101_01010101, 0x01010101_01010101, 0) == [0x01010101_01010101, 0x01010101_01010101] ; run: %ishl(0x01010101_01010101, 0x01010101_01010101, 0) == [0x01010101_01010101, 0x01010101_01010101]
; run: %ishl(0x01010101_01010101, 0x01010101_01010101, 128) == [0x01010101_01010101, 0x01010101_01010101] ; run: %ishl(0x01010101_01010101, 0x01010101_01010101, 128) == [0x01010101_01010101, 0x01010101_01010101]
; run: %ishl(0x00000000_00000001, 0x00000000_00000000, 0) == [0x00000000_00000001, 0x00000000_00000000]
; run: %ishl(0x00000000_00000000, 0x00000000_00000001, 0) == [0x00000000_00000000, 0x00000000_00000001]
; run: %ishl(0x12340000_00000000, 0x56780000_00000000, 0) == [0x12340000_00000000, 0x56780000_00000000]
; run: %ishl(0x12340000_00000000, 0x56780000_00000000, 64) == [0x00000000_00000000, 0x12340000_00000000]
; run: %ishl(0x12340000_00000000, 0x56780000_00000000, 32) == [0x00000000_00000000, 0x00000000_12340000]
function %ushr(i64, i64, i8) -> i64, i64 { function %ushr(i64, i64, i8) -> i64, i64 {
block0(v0: i64, v1: i64, v2: i8): block0(v0: i64, v1: i64, v2: i8):
@@ -26,6 +31,11 @@ block0(v0: i64, v1: i64, v2: i8):
; run: %ushr(0x01010101_01010101, 0x01010101_01010101, 66) == [0x00404040_40404040, 0x00000000_00000000] ; run: %ushr(0x01010101_01010101, 0x01010101_01010101, 66) == [0x00404040_40404040, 0x00000000_00000000]
; run: %ushr(0x01010101_01010101, 0x01010101_01010101, 0) == [0x01010101_01010101, 0x01010101_01010101] ; run: %ushr(0x01010101_01010101, 0x01010101_01010101, 0) == [0x01010101_01010101, 0x01010101_01010101]
; run: %ushr(0x01010101_01010101, 0x01010101_01010101, 128) == [0x01010101_01010101, 0x01010101_01010101] ; run: %ushr(0x01010101_01010101, 0x01010101_01010101, 128) == [0x01010101_01010101, 0x01010101_01010101]
; run: %ushr(0x00000000_00000001, 0x00000000_00000000, 0) == [0x00000000_00000001, 0x00000000_00000000]
; run: %ushr(0x00000000_00000000, 0x00000000_00000001, 0) == [0x00000000_00000000, 0x00000000_00000001]
; run: %ushr(0x12340000_00000000, 0x56780000_00000000, 0) == [0x12340000_00000000, 0x56780000_00000000]
; run: %ushr(0x12340000_00000000, 0x56780000_00000000, 64) == [0x56780000_00000000, 0x00000000_00000000]
; run: %ushr(0x12340000_00000000, 0x56780000_00000000, 32) == [0x00000000_12340000, 0x00000000_56780000]
function %sshr(i64, i64, i8) -> i64, i64 { function %sshr(i64, i64, i8) -> i64, i64 {
block0(v0: i64, v1: i64, v2: i8): block0(v0: i64, v1: i64, v2: i8):
@@ -48,8 +58,8 @@ block0(v0: i64, v1: i64, v2: i8):
} }
; run: %rotl(0x01010101_01010101, 0x01010101_01010101, 9) == [0x02020202_02020202, 0x02020202_02020202] ; run: %rotl(0x01010101_01010101, 0x01010101_01010101, 9) == [0x02020202_02020202, 0x02020202_02020202]
; run: %rotl(0x01010101_01010101, 0x01010101_01010101, 73) == [0x02020202_02020202, 0x02020202_02020202] ; run: %rotl(0x01010101_01010101, 0x01010101_01010101, 73) == [0x02020202_02020202, 0x02020202_02020202]
; run: %rotl(0x01010101_01010101, 0x01010101_01010101, 0) == [0x01010101_01010101, 0x01010101_01010101] ; run: %rotl(0x01010101_01010101, 0x02020202_02020202, 0) == [0x01010101_01010101, 0x02020202_02020202]
; run: %rotl(0x01010101_01010101, 0x01010101_01010101, 128) == [0x01010101_01010101, 0x01010101_01010101] ; run: %rotl(0x01010101_01010101, 0x03030303_03030303, 128) == [0x01010101_01010101, 0x03030303_03030303]
function %rotr(i64, i64, i8) -> i64, i64 { function %rotr(i64, i64, i8) -> i64, i64 {
block0(v0: i64, v1: i64, v2: i8): block0(v0: i64, v1: i64, v2: i8):
@@ -60,5 +70,5 @@ block0(v0: i64, v1: i64, v2: i8):
} }
; run: %rotr(0x01010101_01010101, 0x01010101_01010101, 9) == [0x80808080_80808080, 0x80808080_80808080] ; run: %rotr(0x01010101_01010101, 0x01010101_01010101, 9) == [0x80808080_80808080, 0x80808080_80808080]
; run: %rotr(0x01010101_01010101, 0x01010101_01010101, 73) == [0x80808080_80808080, 0x80808080_80808080] ; run: %rotr(0x01010101_01010101, 0x01010101_01010101, 73) == [0x80808080_80808080, 0x80808080_80808080]
; run: %rotr(0x01010101_01010101, 0x01010101_01010101, 0) == [0x01010101_01010101, 0x01010101_01010101] ; run: %rotr(0x01010101_01010101, 0x02020202_02020202, 0) == [0x01010101_01010101, 0x02020202_02020202]
; run: %rotr(0x01010101_01010101, 0x01010101_01010101, 128) == [0x01010101_01010101, 0x01010101_01010101] ; run: %rotr(0x01010101_01010101, 0x03030303_03030303, 128) == [0x01010101_01010101, 0x03030303_03030303]