x86-64 Windows fastcall ABI support.
This adds support for the "fastcall" ABI, which is the native C/C++ ABI on Windows platforms on x86-64. It is similar to but not exactly like System V; primarily, its argument register assignments are different, and it requires stack shadow space. Note that this also adjusts the handling of multi-register values in the shared ABI implementation, and with this change, adjusts handling of `i128`s on *both* Fastcall/x64 *and* SysV/x64 platforms. This was done to align with actual behavior by the "rustc ABI" on both platforms, as mapped out experimentally (Compiler Explorer link in comments). This behavior is gated under the `enable_llvm_abi_extensions` flag. Note also that this does *not* add x64 unwind info on Windows. That will come in a future PR (but is planned!).
This commit is contained in:
Chris Fallin
299
cranelift/filetests/filetests/isa/x64/fastcall.clif
Normal file
299
cranelift/filetests/filetests/isa/x64/fastcall.clif
Normal file
@@ -0,0 +1,299 @@
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test compile
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set enable_llvm_abi_extensions=true
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target x86_64
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feature "experimental_x64"
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function %f0(i64, i64, i64, i64) -> i64 windows_fastcall {
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block0(v0: i64, v1: i64, v2: i64, v3: i64):
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return v0
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}
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; check: pushq %rbp
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; nextln: movq %rsp, %rbp
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; nextln: movq %rcx, %rax
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; nextln: movq %rbp, %rsp
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; nextln: popq %rbp
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; nextln: ret
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function %f1(i64, i64, i64, i64) -> i64 windows_fastcall {
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block0(v0: i64, v1: i64, v2: i64, v3: i64):
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return v1
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}
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; check: pushq %rbp
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; nextln: movq %rsp, %rbp
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; nextln: movq %rdx, %rax
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; nextln: movq %rbp, %rsp
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; nextln: popq %rbp
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; nextln: ret
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function %f2(i64, i64, i64, i64) -> i64 windows_fastcall {
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block0(v0: i64, v1: i64, v2: i64, v3: i64):
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return v2
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}
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; check: pushq %rbp
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; nextln: movq %rsp, %rbp
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; nextln: movq %r8, %rax
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; nextln: movq %rbp, %rsp
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; nextln: popq %rbp
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; nextln: ret
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function %f3(i64, i64, i64, i64) -> i64 windows_fastcall {
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block0(v0: i64, v1: i64, v2: i64, v3: i64):
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return v3
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}
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; check: pushq %rbp
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; nextln: movq %rsp, %rbp
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; nextln: movq %r9, %rax
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; nextln: movq %rbp, %rsp
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; nextln: popq %rbp
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; nextln: ret
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function %f4(i64, i64, f64, i64) -> f64 windows_fastcall {
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block0(v0: i64, v1: i64, v2: f64, v3: i64):
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return v2
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}
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; check: pushq %rbp
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; nextln: movq %rsp, %rbp
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; nextln: movaps %xmm2, %xmm0
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; nextln: movq %rbp, %rsp
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; nextln: popq %rbp
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; nextln: ret
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function %f5(i64, i64, f64, i64) -> i64 windows_fastcall {
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block0(v0: i64, v1: i64, v2: f64, v3: i64):
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return v3
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}
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; check: pushq %rbp
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; nextln: movq %rsp, %rbp
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; nextln: movq %r9, %rax
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; nextln: movq %rbp, %rsp
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; nextln: popq %rbp
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; nextln: ret
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function %f6(i64, i64, i64, i64, i64, i64) -> i64 windows_fastcall {
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block0(v0: i64, v1: i64, v2: i64, v3: i64, v4: i64, v5: i64):
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return v5
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}
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;; This is truly odd (because of the regalloc ordering), but it works. Note
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;; that we're spilling and using rsi, which is a callee-save in fastcall, because
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;; the regalloc order is optimized for SysV. Also note that because we copy args
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;; out of their input locations to separate vregs, we have a spurious load
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;; from [rbp+48]. Ordinarily these moves are coalesced because the dest vreg
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;; is allocated as a caller-save (volatile), but here again we allocate rsi
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;; first and so have to spill it (and consequently don't coalesce).
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;;
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;; TODO(#2704): fix regalloc's register priority ordering!
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; check: pushq %rbp
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; nextln: movq %rsp, %rbp
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; nextln: subq $$16, %rsp
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; nextln: movq %rsi, 0(%rsp)
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; nextln: virtual_sp_offset_adjust 16
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; nextln: movq 48(%rbp), %rsi
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; nextln: movq 56(%rbp), %rsi
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; nextln: movq %rsi, %rax
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; nextln: movq 0(%rsp), %rsi
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; nextln: addq $$16, %rsp
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; nextln: movq %rbp, %rsp
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; nextln: popq %rbp
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; nextln: ret
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function %f7(i128, i64, i128, i128) -> i128 windows_fastcall {
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block0(v0: i128, v1: i64, v2: i128, v3: i128):
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return v3
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}
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;; Again, terrible regalloc behavior. The important part is that `v3` comes
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;; from [rbp+56] and [rbp+64], i.e., the second and third non-shadow
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;; stack slot.
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; check: pushq %rbp
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; nextln: movq %rsp, %rbp
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; nextln: subq $$16, %rsp
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; nextln: movq %rsi, 0(%rsp)
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; nextln: movq %rdi, 8(%rsp)
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; nextln: virtual_sp_offset_adjust 16
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; nextln: movq 48(%rbp), %rsi
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; nextln: movq 56(%rbp), %rsi
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; nextln: movq 64(%rbp), %rdi
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; nextln: movq %rsi, %rax
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; nextln: movq %rdi, %rdx
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; nextln: movq 0(%rsp), %rsi
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; nextln: movq 8(%rsp), %rdi
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; nextln: addq $$16, %rsp
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; nextln: movq %rbp, %rsp
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; nextln: popq %rbp
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; nextln: ret
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function %f8(i64) -> i64 windows_fastcall {
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sig0 = (i64, i64, f64, f64, i64, i64) -> i64 windows_fastcall
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fn0 = %g sig0
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block0(v0: i64):
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v1 = fcvt_from_sint.f64 v0
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v2 = call fn0(v0, v0, v1, v1, v0, v0)
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return v2
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}
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; check: pushq %rbp
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; nextln: movq %rsp, %rbp
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; nextln: subq $$16, %rsp
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; nextln: movq %rsi, 0(%rsp)
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; nextln: virtual_sp_offset_adjust 16
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; nextln: movq %rcx, %rsi
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; nextln: cvtsi2sd %rsi, %xmm3
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; nextln: subq $$48, %rsp
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; nextln: virtual_sp_offset_adjust 48
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; nextln: movq %rsi, %rcx
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; nextln: movq %rsi, %rdx
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; nextln: movaps %xmm3, %xmm2
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; nextln: movq %rsi, 32(%rsp)
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; nextln: movq %rsi, 40(%rsp)
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; nextln: load_ext_name %g+0, %rsi
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; nextln: call *%rsi
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; nextln: addq $$48, %rsp
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; nextln: virtual_sp_offset_adjust -48
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; nextln: movq 0(%rsp), %rsi
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; nextln: addq $$16, %rsp
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; nextln: movq %rbp, %rsp
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; nextln: popq %rbp
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; nextln: ret
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function %f9(i64) -> f64 windows_fastcall {
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block0(v0: i64):
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v1 = load.f64 v0+0
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v2 = load.f64 v0+8
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v3 = load.f64 v0+16
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v4 = load.f64 v0+24
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v5 = load.f64 v0+32
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v6 = load.f64 v0+40
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v7 = load.f64 v0+48
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v8 = load.f64 v0+56
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v9 = load.f64 v0+64
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v10 = load.f64 v0+72
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v11 = load.f64 v0+80
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v12 = load.f64 v0+88
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v13 = load.f64 v0+96
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v14 = load.f64 v0+104
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v15 = load.f64 v0+112
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v16 = load.f64 v0+120
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v17 = load.f64 v0+128
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v18 = load.f64 v0+136
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v19 = load.f64 v0+144
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v20 = load.f64 v0+152
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v21 = fadd.f64 v1, v2
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v22 = fadd.f64 v3, v4
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v23 = fadd.f64 v5, v6
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v24 = fadd.f64 v7, v8
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v25 = fadd.f64 v9, v10
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v26 = fadd.f64 v11, v12
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v27 = fadd.f64 v13, v14
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v28 = fadd.f64 v15, v16
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v29 = fadd.f64 v17, v18
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v30 = fadd.f64 v19, v20
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v31 = fadd.f64 v21, v22
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v32 = fadd.f64 v23, v24
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v33 = fadd.f64 v25, v26
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v34 = fadd.f64 v27, v28
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v35 = fadd.f64 v29, v30
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v36 = fadd.f64 v31, v32
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v37 = fadd.f64 v33, v34
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v38 = fadd.f64 v36, v37
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v39 = fadd.f64 v38, v35
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return v39
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}
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; check: pushq %rbp
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; nextln: movq %rsp, %rbp
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; nextln: subq $$208, %rsp
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; nextln: movdqu %xmm6, 0(%rsp)
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; nextln: movdqu %xmm7, 16(%rsp)
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; nextln: movdqu %xmm8, 32(%rsp)
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; nextln: movdqu %xmm9, 48(%rsp)
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; nextln: movdqu %xmm10, 64(%rsp)
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; nextln: movdqu %xmm11, 80(%rsp)
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; nextln: movdqu %xmm12, 96(%rsp)
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; nextln: movdqu %xmm13, 112(%rsp)
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; nextln: movdqu %xmm14, 128(%rsp)
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; nextln: movdqu %xmm15, 144(%rsp)
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; nextln: virtual_sp_offset_adjust 160
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; nextln: movsd 0(%rcx), %xmm0
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; nextln: movsd %xmm0, rsp(16 + virtual offset)
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; nextln: movsd 8(%rcx), %xmm1
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; nextln: movsd 16(%rcx), %xmm0
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; nextln: movsd %xmm0, rsp(24 + virtual offset)
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; nextln: movsd 24(%rcx), %xmm3
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; nextln: movsd 32(%rcx), %xmm0
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; nextln: movsd %xmm0, rsp(32 + virtual offset)
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; nextln: movsd 40(%rcx), %xmm5
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; nextln: movsd 48(%rcx), %xmm6
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; nextln: movsd 56(%rcx), %xmm7
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; nextln: movsd 64(%rcx), %xmm8
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; nextln: movsd 72(%rcx), %xmm9
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; nextln: movsd 80(%rcx), %xmm10
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; nextln: movsd 88(%rcx), %xmm11
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; nextln: movsd 96(%rcx), %xmm12
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; nextln: movsd 104(%rcx), %xmm13
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; nextln: movsd 112(%rcx), %xmm14
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; nextln: movsd 120(%rcx), %xmm15
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; nextln: movsd 128(%rcx), %xmm0
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; nextln: movsd %xmm0, rsp(0 + virtual offset)
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; nextln: movsd 136(%rcx), %xmm0
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; nextln: movsd 144(%rcx), %xmm2
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; nextln: movsd %xmm2, rsp(8 + virtual offset)
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; nextln: movsd 152(%rcx), %xmm2
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; nextln: nop len=0
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; nextln: movsd rsp(16 + virtual offset), %xmm4
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; nextln: addsd %xmm1, %xmm4
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; nextln: movsd %xmm4, rsp(16 + virtual offset)
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; nextln: movsd rsp(24 + virtual offset), %xmm1
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; nextln: addsd %xmm3, %xmm1
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; nextln: movsd rsp(32 + virtual offset), %xmm4
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; nextln: addsd %xmm5, %xmm4
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; nextln: addsd %xmm7, %xmm6
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; nextln: addsd %xmm9, %xmm8
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; nextln: addsd %xmm11, %xmm10
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; nextln: addsd %xmm13, %xmm12
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; nextln: addsd %xmm15, %xmm14
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; nextln: movsd rsp(0 + virtual offset), %xmm3
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; nextln: addsd %xmm0, %xmm3
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; nextln: movsd rsp(8 + virtual offset), %xmm0
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; nextln: addsd %xmm2, %xmm0
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; nextln: movsd rsp(16 + virtual offset), %xmm2
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; nextln: addsd %xmm1, %xmm2
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; nextln: addsd %xmm6, %xmm4
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; nextln: addsd %xmm10, %xmm8
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; nextln: addsd %xmm14, %xmm12
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; nextln: addsd %xmm0, %xmm3
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; nextln: addsd %xmm4, %xmm2
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; nextln: addsd %xmm12, %xmm8
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; nextln: addsd %xmm8, %xmm2
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; nextln: addsd %xmm3, %xmm2
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; nextln: movaps %xmm2, %xmm0
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; nextln: movdqu 0(%rsp), %xmm6
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; nextln: movdqu 16(%rsp), %xmm7
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; nextln: movdqu 32(%rsp), %xmm8
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; nextln: movdqu 48(%rsp), %xmm9
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; nextln: movdqu 64(%rsp), %xmm10
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; nextln: movdqu 80(%rsp), %xmm11
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; nextln: movdqu 96(%rsp), %xmm12
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; nextln: movdqu 112(%rsp), %xmm13
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; nextln: movdqu 128(%rsp), %xmm14
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; nextln: movdqu 144(%rsp), %xmm15
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; nextln: addq $$160, %rsp
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; nextln: movq %rbp, %rsp
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; nextln: popq %rbp
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; nextln: ret
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@@ -1,4 +1,5 @@
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test compile
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set enable_llvm_abi_extensions=true
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target x86_64
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feature "experimental_x64"
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@@ -941,17 +942,17 @@ block0(v0: i128, v1: i128, v2: i64, v3: i128, v4: i128, v5: i128):
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v11 = iadd.i128 v9, v10
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return v11
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; check: movq %rsp, %rbp
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; check: pushq %rbp
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; nextln: movq %rsp, %rbp
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; nextln: subq $$16, %rsp
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; nextln: movq %r12, 0(%rsp)
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; nextln: movq %r13, 8(%rsp)
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; nextln: virtual_sp_offset_adjust 16
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; nextln: movq 16(%rbp), %r9
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; nextln: movq 24(%rbp), %r10
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; nextln: movq 32(%rbp), %r12
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; nextln: movq 40(%rbp), %r11
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; nextln: movq 48(%rbp), %rax
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; nextln: movq 56(%rbp), %r13
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; nextln: movq 16(%rbp), %r10
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; nextln: movq 24(%rbp), %r12
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; nextln: movq 32(%rbp), %r11
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; nextln: movq 40(%rbp), %rax
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; nextln: movq 48(%rbp), %r13
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; nextln: addq %rdx, %rdi
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; nextln: adcq %rcx, %rsi
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; nextln: xorq %rcx, %rcx
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@@ -989,10 +990,10 @@ block0(v0: i128):
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; nextln: movq %r10, 16(%rsi)
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; nextln: movq %r11, 24(%rsi)
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; nextln: movq %r12, 32(%rsi)
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; nextln: movq %r13, 48(%rsi)
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; nextln: movq %r14, 56(%rsi)
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; nextln: movq %rdi, 64(%rsi)
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; nextln: movq %rbx, 72(%rsi)
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; nextln: movq %r13, 40(%rsi)
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; nextln: movq %r14, 48(%rsi)
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; nextln: movq %rdi, 56(%rsi)
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; nextln: movq %rbx, 64(%rsi)
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}
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@@ -1,4 +1,5 @@
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test compile
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set enable_llvm_abi_extensions=true
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target x86_64
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feature "experimental_x64"
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