diff --git a/build.rs b/build.rs
index 9864d44570..b1dda8abf2 100644
--- a/build.rs
+++ b/build.rs
@@ -199,9 +199,11 @@ fn experimental_x64_should_panic(testsuite: &str, testname: &str, strategy: &str
         ("simd", "simd_f32x4") => return false,
         ("simd", "simd_f32x4_arith") => return false,
         ("simd", "simd_f32x4_cmp") => return false,
+        ("simd", "simd_f32x4_pmin_pmax") => return false,
         ("simd", "simd_f64x2") => return false,
         ("simd", "simd_f64x2_arith") => return false,
         ("simd", "simd_f64x2_cmp") => return false,
+        ("simd", "simd_f64x2_pmin_pmax") => return false,
         ("simd", "simd_lane") => return false,
         ("simd", "simd_load_splat") => return false,
         ("simd", "simd_store") => return false,
@@ -231,16 +233,15 @@ fn ignore(testsuite: &str, testname: &str, strategy: &str) -> bool {
             }
 
             // These are only implemented on aarch64 and x64.
-            ("simd", "simd_boolean") => {
+            ("simd", "simd_boolean")
+            | ("simd", "simd_f32x4_pmin_pmax")
+            | ("simd", "simd_f64x2_pmin_pmax") => {
                 return !(cfg!(feature = "experimental_x64")
                     || env::var("CARGO_CFG_TARGET_ARCH").unwrap() == "aarch64")
             }
 
             // These are only implemented on aarch64.
-            ("simd", "simd_f32x4_pmin_pmax")
-            | ("simd", "simd_f32x4_rounding")
-            | ("simd", "simd_f64x2_pmin_pmax")
-            | ("simd", "simd_f64x2_rounding") => {
+            ("simd", "simd_f32x4_rounding") | ("simd", "simd_f64x2_rounding") => {
                 return env::var("CARGO_CFG_TARGET_ARCH").unwrap() != "aarch64";
             }
 
diff --git a/cranelift/codegen/src/isa/x64/lower.rs b/cranelift/codegen/src/isa/x64/lower.rs
index f63a157d8c..d7c21d292e 100644
--- a/cranelift/codegen/src/isa/x64/lower.rs
+++ b/cranelift/codegen/src/isa/x64/lower.rs
@@ -2167,6 +2167,22 @@ fn lower_insn_to_regs<C: LowerCtx<I = Inst>>(
             }
         }
 
+        Opcode::FminPseudo | Opcode::FmaxPseudo => {
+            let lhs = input_to_reg_mem(ctx, inputs[0]);
+            let rhs = put_input_in_reg(ctx, inputs[1]);
+            let dst = get_output_reg(ctx, outputs[0]);
+            let ty = ty.unwrap();
+            ctx.emit(Inst::gen_move(dst, rhs, ty));
+            let sse_opcode = match (ty, op) {
+                (types::F32X4, Opcode::FminPseudo) => SseOpcode::Minps,
+                (types::F32X4, Opcode::FmaxPseudo) => SseOpcode::Maxps,
+                (types::F64X2, Opcode::FminPseudo) => SseOpcode::Minpd,
+                (types::F64X2, Opcode::FmaxPseudo) => SseOpcode::Maxpd,
+                _ => unimplemented!("unsupported type {} for {}", ty, op),
+            };
+            ctx.emit(Inst::xmm_rm_r(sse_opcode, lhs, dst, None));
+        }
+
         Opcode::Sqrt => {
             let src = input_to_reg_mem(ctx, inputs[0]);
             let dst = get_output_reg(ctx, outputs[0]);