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Enable the simd_conversions test for AArch64

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Copyright (c) 2021, Arm Limited.
This commit is contained in:
Anton Kirilov
2021-06-02 19:54:34 +01:00
parent ff1ae6e10c
commit 6c3d7092b9
5 changed files with 97 additions and 8 deletions
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16
cranelift/codegen/src/isa/aarch64/inst/mod.rs
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@@ -396,6 +396,10 @@ pub enum VecRRNarrowOp {
Uqxtn32,
/// Unsigned saturating extract narrow, 64-bit elements
Uqxtn64,
/// Floating-point convert to lower precision narrow, 32-bit elements
Fcvtn32,
/// Floating-point convert to lower precision narrow, 64-bit elements
Fcvtn64,
}
/// A vector operation on a pair of elements with one register.
@@ -4073,6 +4077,18 @@ impl Inst {
(VecRRNarrowOp::Uqxtn64, true) => {
("uqxtn2", VectorSize::Size32x4, VectorSize::Size64x2)
}
(VecRRNarrowOp::Fcvtn32, false) => {
("fcvtn", VectorSize::Size16x4, VectorSize::Size32x4)
}
(VecRRNarrowOp::Fcvtn32, true) => {
("fcvtn2", VectorSize::Size16x8, VectorSize::Size32x4)
}
(VecRRNarrowOp::Fcvtn64, false) => {
("fcvtn", VectorSize::Size32x2, VectorSize::Size64x2)
}
(VecRRNarrowOp::Fcvtn64, true) => {
("fcvtn2", VectorSize::Size32x4, VectorSize::Size64x2)
}
};
let rd = show_vreg_vector(rd.to_reg(), mb_rru, rd_size);
let rn = show_vreg_vector(rn, mb_rru, size);