T0b1/wasmtime
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Enable the simd_conversions test for AArch64

Browse Source 
Copyright (c) 2021, Arm Limited.
This commit is contained in:
Anton Kirilov
2021-06-02 19:54:34 +01:00
parent ff1ae6e10c
commit 6c3d7092b9
5 changed files with 97 additions and 8 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
cranelift/codegen/src/isa/aarch64/inst/emit.rs
View File

@@ -2128,6 +2128,8 @@ impl MachInstEmit for Inst {
VecRRNarrowOp::Uqxtn16 => (0b1, 0b00, 0b10100),
VecRRNarrowOp::Uqxtn32 => (0b1, 0b01, 0b10100),
VecRRNarrowOp::Uqxtn64 => (0b1, 0b10, 0b10100),
VecRRNarrowOp::Fcvtn32 => (0b0, 0b00, 0b10110),
VecRRNarrowOp::Fcvtn64 => (0b0, 0b01, 0b10110),
};
sink.put4(enc_vec_rr_misc(

22
cranelift/codegen/src/isa/aarch64/inst/emit_tests.rs
View File

@@ -2611,6 +2611,28 @@ fn test_aarch64_binemit() {
"uqxtn2 v11.4s, v12.2d",
));
insns.push((
Inst::VecRRNarrow {
op: VecRRNarrowOp::Fcvtn32,
rd: writable_vreg(0),
rn: vreg(0),
high_half: false,
},
"0068210E",
"fcvtn v0.4h, v0.4s",
));
insns.push((
Inst::VecRRNarrow {
op: VecRRNarrowOp::Fcvtn64,
rd: writable_vreg(31),
rn: vreg(30),
high_half: true,
},
"DF6B614E",
"fcvtn2 v31.4s, v30.2d",
));
insns.push((
Inst::VecRRPair {
op: VecPairOp::Addp,

16
cranelift/codegen/src/isa/aarch64/inst/mod.rs
View File

@@ -396,6 +396,10 @@ pub enum VecRRNarrowOp {
Uqxtn32,
/// Unsigned saturating extract narrow, 64-bit elements
Uqxtn64,
/// Floating-point convert to lower precision narrow, 32-bit elements
Fcvtn32,
/// Floating-point convert to lower precision narrow, 64-bit elements
Fcvtn64,
}
/// A vector operation on a pair of elements with one register.
@@ -4073,6 +4077,18 @@ impl Inst {
(VecRRNarrowOp::Uqxtn64, true) => {
("uqxtn2", VectorSize::Size32x4, VectorSize::Size64x2)
}
(VecRRNarrowOp::Fcvtn32, false) => {
("fcvtn", VectorSize::Size16x4, VectorSize::Size32x4)
}
(VecRRNarrowOp::Fcvtn32, true) => {
("fcvtn2", VectorSize::Size16x8, VectorSize::Size32x4)
}
(VecRRNarrowOp::Fcvtn64, false) => {
("fcvtn", VectorSize::Size32x2, VectorSize::Size64x2)
}
(VecRRNarrowOp::Fcvtn64, true) => {
("fcvtn2", VectorSize::Size32x4, VectorSize::Size64x2)
}
};
let rd = show_vreg_vector(rd.to_reg(), mb_rru, rd_size);
let rn = show_vreg_vector(rn, mb_rru, size);