Disallow branching to the entry block.

Functions that would otherwise start with a loop should start with a
separate ebb which just branches to the header of the loop.

cranelift/filetests/licm/basic.cton

@@ -2,30 +2,33 @@ test licm
 
 function %simple_loop(i32) -> i32 {
 
-ebb1(v0: i32):
-    v1 = iconst.i32 1
-    v2 = iconst.i32 2
-    v3 = iadd v1, v2
-    brz v0, ebb2(v0)
-    v4 = isub v0, v1
-    jump ebb1(v4)
+ebb0(v0: i32):
+    jump ebb1(v0)
 
-ebb2(v5: i32):
-    return v5
+ebb1(v1: i32):
+    v2 = iconst.i32 1
+    v3 = iconst.i32 2
+    v4 = iadd v2, v3
+    brz v1, ebb2(v1)
+    v5 = isub v1, v2
+    jump ebb1(v5)
+
+ebb2(v6: i32):
+    return v6
 
 }
 ; sameln: function %simple_loop
-; nextln: ebb2(v6: i32):
-; nextln:     v1 = iconst.i32 1
-; nextln:     v2 = iconst.i32 2
-; nextln:     v3 = iadd v1, v2
-; nextln:     jump ebb0(v6)
-; nextln: 
 ; nextln: ebb0(v0: i32):
-; nextln:     brz v0, ebb1(v0)
-; nextln:     v4 = isub v0, v1
-; nextln:     jump ebb0(v4)
+; nextln:     v2 = iconst.i32 1
+; nextln:     v3 = iconst.i32 2
+; nextln:     v4 = iadd v2, v3
+; nextln:     jump ebb1(v0)
 ; nextln: 
-; nextln: ebb1(v5: i32):
-; nextln:     return v5
+; nextln: ebb1(v1: i32):
+; nextln:     brz v1, ebb2(v1)
+; nextln:     v5 = isub v1, v2
+; nextln:     jump ebb1(v5)
+; nextln: 
+; nextln: ebb2(v6: i32):
+; nextln:     return v6
 ; nextln: }

cranelift/filetests/licm/complex.cton

@@ -1,81 +1,83 @@
 test licm
 
-function %complex(i32) -> i32 {
-
+function %complex(i32) -> i32 native {
 ebb0(v0: i32):
-    v1 = iconst.i32 1
-    v19 = iconst.i32 4
-    v2 = iadd v1, v0
-    brz v0, ebb1(v1)
-    jump ebb3(v2)
+    jump ebb1(v0)
 
-ebb1(v3: i32):
-    v4 = iconst.i32 2
-    v5 = iadd v3, v2
-    v6 = iadd v4, v0
-    jump ebb2(v6)
+ebb1(v1: i32):
+    v2 = iconst.i32 1
+    v3 = iconst.i32 4
+    v4 = iadd v2, v1
+    brz v1, ebb2(v2)
+    jump ebb4(v4)
 
-ebb2(v7: i32):
-    v8 = iadd v7, v3
-    v9 = iadd v0, v2
-    brz v0, ebb1(v7)
-    jump ebb5(v8)
+ebb2(v5: i32):
+    v6 = iconst.i32 2
+    v7 = iadd v5, v4
+    v8 = iadd v6, v1
+    jump ebb3(v8)
 
-ebb3(v10: i32):
-    v11 = iconst.i32 3
-    v12 = iadd v10, v11
-    v13 = iadd v2, v11
-    jump ebb4(v11)
+ebb3(v9: i32):
+    v10 = iadd v9, v5
+    v11 = iadd.i32 v1, v4
+    brz.i32 v1, ebb2(v9)
+    jump ebb6(v10)
 
-ebb4(v14: i32):
-    v15 = iadd v12, v2
-    brz v0, ebb3(v14)
-    jump ebb5(v14)
+ebb4(v12: i32):
+    v13 = iconst.i32 3
+    v14 = iadd v12, v13
+    v15 = iadd.i32 v4, v13
+    jump ebb5(v13)
 
 ebb5(v16: i32):
-    v17 = iadd v16, v1
-    v18 = iadd v1, v19
-    brz v0, ebb0(v18)
-    return v17
+    v17 = iadd.i32 v14, v4
+    brz.i32 v1, ebb4(v16)
+    jump ebb6(v16)
+
+ebb6(v18: i32):
+    v19 = iadd v18, v2
+    v20 = iadd.i32 v2, v3
+    brz.i32 v1, ebb1(v20)
+    return v19
 }
 
 ; sameln: function %complex
-; nextln: ebb6(v20: i32):
-; nextln:     v1 = iconst.i32 1
-; nextln:     v2 = iconst.i32 4
-; nextln:     v5 = iconst.i32 2
-; nextln:     v12 = iconst.i32 3
-; nextln:     v19 = iadd v1, v2
-; nextln:     jump ebb0(v20)
-; nextln: 
 ; nextln: ebb0(v0: i32):
-; nextln:     v3 = iadd.i32 v1, v0
-; nextln:     v7 = iadd.i32 v5, v0
-; nextln:     v10 = iadd v0, v3
-; nextln:     brz v0, ebb1(v1)
-; nextln:     v14 = iadd v3, v12
-; nextln:     jump ebb3(v3)
+; nextln:     v2 = iconst.i32 1
+; nextln:     v3 = iconst.i32 4
+; nextln:     v6 = iconst.i32 2
+; nextln:     v13 = iconst.i32 3
+; nextln:     v20 = iadd v2, v3
+; nextln:     jump ebb1(v0)
 ; nextln: 
-; nextln: ebb1(v4: i32):
-; nextln:     v6 = iadd v4, v3
-; nextln:     jump ebb2(v7)
+; nextln: ebb1(v1: i32):
+; nextln:     v4 = iadd.i32 v2, v1
+; nextln:     v8 = iadd.i32 v6, v1
+; nextln:     v11 = iadd v1, v4
+; nextln:     brz v1, ebb2(v2)
+; nextln:     v15 = iadd v4, v13
+; nextln:     jump ebb4(v4)
 ; nextln: 
-; nextln: ebb2(v8: i32):
-; nextln:     v9 = iadd v8, v4
-; nextln:     brz.i32 v0, ebb1(v8)
-; nextln:     jump ebb5(v9)
+; nextln: ebb2(v5: i32):
+; nextln:     v7 = iadd v5, v4
+; nextln:     jump ebb3(v8)
 ; nextln: 
-; nextln: ebb3(v11: i32):
-; nextln:     v13 = iadd v11, v12
-; nextln:     jump ebb4(v12)
+; nextln: ebb3(v9: i32):
+; nextln:     v10 = iadd v9, v5
+; nextln:     brz.i32 v1, ebb2(v9)
+; nextln:     jump ebb6(v10)
 ; nextln: 
-; nextln: ebb4(v15: i32):
-; nextln:     v16 = iadd.i32 v13, v3
-; nextln:     brz.i32 v0, ebb3(v15)
-; nextln:     jump ebb5(v15)
+; nextln: ebb4(v12: i32):
+; nextln:     v14 = iadd v12, v13
+; nextln:     jump ebb5(v13)
 ; nextln: 
-; nextln: ebb5(v17: i32):
-; nextln:     v18 = iadd v17, v1
-; nextln:     brz.i32 v0, ebb0(v19)
-; nextln:     return v18
+; nextln: ebb5(v16: i32):
+; nextln:     v17 = iadd.i32 v14, v4
+; nextln:     brz.i32 v1, ebb4(v16)
+; nextln:     jump ebb6(v16)
+; nextln: 
+; nextln: ebb6(v18: i32):
+; nextln:     v19 = iadd v18, v2
+; nextln:     brz.i32 v1, ebb1(v20)
+; nextln:     return v19
 ; nextln: }

cranelift/filetests/licm/nested_loops.cton

@@ -3,50 +3,53 @@ test licm
 function %nested_loops(i32) -> i32 {
 
 ebb0(v0: i32):
-    v1 = iconst.i32 1
-    v2 = iconst.i32 2
-    v3 = iadd v1, v2
-    v4 = isub v0, v1
-    jump ebb1(v4,v4)
+    jump ebb1(v0)
 
-ebb1(v10: i32,v11: i32):
-    brz v11, ebb2(v10)
+ebb1(v1: i32):
+    v2 = iconst.i32 1
+    v3 = iconst.i32 2
+    v4 = iadd v2, v3
+    v5 = isub v1, v2
+    jump ebb2(v5, v5)
+
+ebb2(v10: i32, v11: i32):
+    brz v11, ebb3(v10)
     v12 = iconst.i32 1
-    v15 = iadd v12, v4
+    v15 = iadd v12, v5
     v13 = isub v11, v12
-    jump ebb1(v10,v13)
+    jump ebb2(v10,v13)
 
-ebb2(v20: i32):
-    brz v20, ebb3(v20)
-    jump ebb0(v20)
+ebb3(v20: i32):
+    brz v20, ebb4(v20)
+    jump ebb1(v20)
 
-ebb3(v30: i32):
+ebb4(v30: i32):
     return v30
 
 }
 
 ; sameln:function %nested_loops(i32) -> i32 {
-; nextln: ebb4(v12: i32):
-; nextln:     v1 = iconst.i32 1
-; nextln:     v2 = iconst.i32 2
-; nextln:     v3 = iadd v1, v2
-; nextln:     v7 = iconst.i32 1
-; nextln:     jump ebb0(v12)
-; nextln: 
 ; nextln: ebb0(v0: i32):
-; nextln:     v4 = isub v0, v1
-; nextln:     v8 = iadd.i32 v7, v4
-; nextln:     jump ebb1(v4, v4)
+; nextln:     v2 = iconst.i32 1
+; nextln:     v3 = iconst.i32 2
+; nextln:     v4 = iadd v2, v3
+; nextln:     v8 = iconst.i32 1
+; nextln:     jump ebb1(v0)
 ; nextln: 
-; nextln: ebb1(v5: i32, v6: i32):
-; nextln:     brz v6, ebb2(v5)
-; nextln:     v9 = isub v6, v7
-; nextln:     jump ebb1(v5, v9)
+; nextln: ebb1(v1: i32):
+; nextln:     v5 = isub v1, v2
+; nextln:     v9 = iadd.i32 v8, v5
+; nextln:     jump ebb2(v5, v5)
 ; nextln: 
-; nextln: ebb2(v10: i32):
-; nextln:     brz v10, ebb3(v10)
-; nextln:     jump ebb0(v10)
+; nextln: ebb2(v6: i32, v7: i32):
+; nextln:     brz v7, ebb3(v6)
+; nextln:     v10 = isub v7, v8
+; nextln:     jump ebb2(v6, v10)
 ; nextln: 
 ; nextln: ebb3(v11: i32):
-; nextln:     return v11
+; nextln:     brz v11, ebb4(v11)
+; nextln:     jump ebb1(v11)
+; nextln: 
+; nextln: ebb4(v12: i32):
+; nextln:     return v12
 ; nextln: }