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Don't reuse destination registers when lowering splat on aarch64 (#5370)

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This commit is contained in:
Trevor Elliott
2022-12-05 08:18:49 -08:00
committed by GitHub
parent a28d4d3c89
commit 6aea8e0d7e
2 changed files with 5 additions and 4 deletions
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5
cranelift/codegen/src/isa/aarch64/inst/mod.rs
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@@ -421,8 +421,9 @@ impl Inst {
size size
}] }]
} else if let Some(imm) = widen_32_bit_pattern(pattern, lane_size) { } else if let Some(imm) = widen_32_bit_pattern(pattern, lane_size) {
let tmp = alloc_tmp(types::I64X2);
let mut insts = smallvec![Inst::VecDupImm { let mut insts = smallvec![Inst::VecDupImm {
rd, rd: tmp,
imm, imm,
invert: false, invert: false,
size: VectorSize::Size64x2, size: VectorSize::Size64x2,
@@ -433,7 +434,7 @@ impl Inst {
if !size.is_128bits() { if !size.is_128bits() {
insts.push(Inst::FpuExtend { insts.push(Inst::FpuExtend {
rd, rd,
rn: rd.to_reg(), rn: tmp.to_reg(),
size: ScalarSize::Size64, size: ScalarSize::Size64,
}); });
} }

4
cranelift/filetests/filetests/isa/aarch64/simd.clif
View File

@@ -101,8 +101,8 @@ block0:
} }
; block0: ; block0:
; movi v0.2d, #18374687579166474495 ; movi v1.2d, #18374687579166474495
; fmov d0, d0 ; fmov d0, d1
; ret ; ret
function %f10() -> i32x4 { function %f10() -> i32x4 {