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Start adding Intel 64-bit encodings.

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Add a TailRecipe.rex() method which creates an encoding recipe with a
REX prefix.

Define I64 encodings with REX.W for i64 operations and with/without REX
for i32 ops. Only test the with-REX encodings for now. We don't yet have
an instruction shrinking pass that can select the non-REX encodings.
This commit is contained in:
Jakob Stoklund Olesen
2017-07-10 16:16:22 -07:00
parent 263779ac56
commit 6ae4eb82f8
4 changed files with 365 additions and 18 deletions
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248
filetests/isa/intel/binary64.cton Normal file
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; binary emission of 64-bit code.
test binemit
set is_64bit
isa intel
; The binary encodings can be verified with the command:
;
; sed -ne 's/^ *; asm: *//p' filetests/isa/intel/binary64.cton | llvm-mc -show-encoding -triple=x86_64
;
; Tests for i64 instructions.
function %I64() {
fn0 = function %foo()
sig0 = signature()
ebb0:
; Integer Constants.
; asm: movq $0x01020304f1f2f3f4, %rcx
[-,%rcx] v1 = iconst.i64 0x0102_0304_f1f2_f3f4 ; bin: 48 b9 01020304f1f2f3f4
; asm: movq $0x11020304f1f2f3f4, %rsi
[-,%rsi] v2 = iconst.i64 0x1102_0304_f1f2_f3f4 ; bin: 48 be 11020304f1f2f3f4
; asm: movq $0x21020304f1f2f3f4, %r10
[-,%r10] v3 = iconst.i64 0x2102_0304_f1f2_f3f4 ; bin: 49 ba 21020304f1f2f3f4
; asm: movl $0xff001122, %r8d # 32-bit zero-extended constant.
[-,%r8] v4 = iconst.i64 0xff00_1122 ; bin: 41 b8 ff001122
; asm: movq $0xffffffff88001122, %r14 # 32-bit sign-extended constant.
[-,%r14] v5 = iconst.i64 0xffff_ffff_8800_1122 ; bin: 49 c7 c6 88001122
; Integer Register-Register Operations.
; asm: addq %rsi, %rcx
[-,%rcx] v10 = iadd v1, v2 ; bin: 48 01 f1
; asm: addq %r10, %rsi
[-,%rsi] v11 = iadd v2, v3 ; bin: 4c 01 d6
; asm: addq %rcx, %r10
[-,%r10] v12 = iadd v3, v1 ; bin: 49 01 ca
; asm: subq %rsi, %rcx
[-,%rcx] v20 = isub v1, v2 ; bin: 48 29 f1
; asm: subq %r10, %rsi
[-,%rsi] v21 = isub v2, v3 ; bin: 4c 29 d6
; asm: subq %rcx, %r10
[-,%r10] v22 = isub v3, v1 ; bin: 49 29 ca
; asm: andq %rsi, %rcx
[-,%rcx] v30 = band v1, v2 ; bin: 48 21 f1
; asm: andq %r10, %rsi
[-,%rsi] v31 = band v2, v3 ; bin: 4c 21 d6
; asm: andq %rcx, %r10
[-,%r10] v32 = band v3, v1 ; bin: 49 21 ca
; asm: orq %rsi, %rcx
[-,%rcx] v40 = bor v1, v2 ; bin: 48 09 f1
; asm: orq %r10, %rsi
[-,%rsi] v41 = bor v2, v3 ; bin: 4c 09 d6
; asm: orq %rcx, %r10
[-,%r10] v42 = bor v3, v1 ; bin: 49 09 ca
; asm: xorq %rsi, %rcx
[-,%rcx] v50 = bxor v1, v2 ; bin: 48 31 f1
; asm: xorq %r10, %rsi
[-,%rsi] v51 = bxor v2, v3 ; bin: 4c 31 d6
; asm: xorq %rcx, %r10
[-,%r10] v52 = bxor v3, v1 ; bin: 49 31 ca
; asm: movq %rsi, %rcx
[-,%rcx] v60 = copy v2 ; bin: 48 89 f1
; asm: movq %r10, %rsi
[-,%rsi] v61 = copy v3 ; bin: 4c 89 d6
; asm: movq %rcx, %r10
[-,%r10] v62 = copy v1 ; bin: 49 89 ca
; Integer Register-Immediate Operations.
; These 64-bit ops all use a 32-bit immediate that is sign-extended to 64 bits.
; Some take 8-bit immediates that are sign-extended to 64 bits.
; asm: addq $-100000, %rcx
[-,%rcx] v70 = iadd_imm v1, -100000 ; bin: 48 81 c1 fffe7960
; asm: addq $100000, %rsi
[-,%rsi] v71 = iadd_imm v2, 100000 ; bin: 48 81 c6 000186a0
; asm: addq $0x7fffffff, %r10
[-,%r10] v72 = iadd_imm v3, 0x7fff_ffff ; bin: 49 81 c2 7fffffff
; asm: addq $100, %r8
[-,%r8] v73 = iadd_imm v4, 100 ; bin: 49 83 c0 64
; asm: addq $-100, %r14
[-,%r14] v74 = iadd_imm v5, -100 ; bin: 49 83 c6 9c
; asm: andq $-100000, %rcx
[-,%rcx] v80 = band_imm v1, -100000 ; bin: 48 81 e1 fffe7960
; asm: andq $100000, %rsi
[-,%rsi] v81 = band_imm v2, 100000 ; bin: 48 81 e6 000186a0
; asm: andq $0x7fffffff, %r10
[-,%r10] v82 = band_imm v3, 0x7fff_ffff ; bin: 49 81 e2 7fffffff
; asm: andq $100, %r8
[-,%r8] v83 = band_imm v4, 100 ; bin: 49 83 e0 64
; asm: andq $-100, %r14
[-,%r14] v84 = band_imm v5, -100 ; bin: 49 83 e6 9c
; asm: orq $-100000, %rcx
[-,%rcx] v90 = bor_imm v1, -100000 ; bin: 48 81 c9 fffe7960
; asm: orq $100000, %rsi
[-,%rsi] v91 = bor_imm v2, 100000 ; bin: 48 81 ce 000186a0
; asm: orq $0x7fffffff, %r10
[-,%r10] v92 = bor_imm v3, 0x7fff_ffff ; bin: 49 81 ca 7fffffff
; asm: orq $100, %r8
[-,%r8] v93 = bor_imm v4, 100 ; bin: 49 83 c8 64
; asm: orq $-100, %r14
[-,%r14] v94 = bor_imm v5, -100 ; bin: 49 83 ce 9c
; asm: ret
; asm: xorq $-100000, %rcx
[-,%rcx] v100 = bxor_imm v1, -100000 ; bin: 48 81 f1 fffe7960
; asm: xorq $100000, %rsi
[-,%rsi] v101 = bxor_imm v2, 100000 ; bin: 48 81 f6 000186a0
; asm: xorq $0x7fffffff, %r10
[-,%r10] v102 = bxor_imm v3, 0x7fff_ffff ; bin: 49 81 f2 7fffffff
; asm: xorq $100, %r8
[-,%r8] v103 = bxor_imm v4, 100 ; bin: 49 83 f0 64
; asm: xorq $-100, %r14
[-,%r14] v104 = bxor_imm v5, -100 ; bin: 49 83 f6 9c
return ; bin: c3
}
; Tests for i32 instructions in 64-bit mode.
;
; Note that many i32 instructions can be encoded both with and without a REX
; prefix if they only use the low 8 registers. Here, we are testing the REX
; encodings which are chosen by default. Switching to non-REX encodings should
; be done by an instruction shrinking pass.
function %I32() {
fn0 = function %foo()
sig0 = signature()
ebb0:
; Integer Constants.
; asm: movl $0x01020304, %ecx
[-,%rcx] v1 = iconst.i32 0x0102_0304 ; bin: 40 b9 01020304
; asm: movl $0x11020304, %esi
[-,%rsi] v2 = iconst.i32 0x1102_0304 ; bin: 40 be 11020304
; asm: movl $0x21020304, %r10d
[-,%r10] v3 = iconst.i32 0x2102_0304 ; bin: 41 ba 21020304
; asm: movl $0xff001122, %r8d
[-,%r8] v4 = iconst.i32 0xff00_1122 ; bin: 41 b8 ff001122
; asm: movl $0x88001122, %r14d
[-,%r14] v5 = iconst.i32 0xffff_ffff_8800_1122 ; bin: 41 be 88001122
; Integer Register-Register Operations.
; asm: addl %esi, %ecx
[-,%rcx] v10 = iadd v1, v2 ; bin: 40 01 f1
; asm: addl %r10d, %esi
[-,%rsi] v11 = iadd v2, v3 ; bin: 44 01 d6
; asm: addl %ecx, %r10d
[-,%r10] v12 = iadd v3, v1 ; bin: 41 01 ca
; asm: subl %esi, %ecx
[-,%rcx] v20 = isub v1, v2 ; bin: 40 29 f1
; asm: subl %r10d, %esi
[-,%rsi] v21 = isub v2, v3 ; bin: 44 29 d6
; asm: subl %ecx, %r10d
[-,%r10] v22 = isub v3, v1 ; bin: 41 29 ca
; asm: andl %esi, %ecx
[-,%rcx] v30 = band v1, v2 ; bin: 40 21 f1
; asm: andl %r10d, %esi
[-,%rsi] v31 = band v2, v3 ; bin: 44 21 d6
; asm: andl %ecx, %r10d
[-,%r10] v32 = band v3, v1 ; bin: 41 21 ca
; asm: orl %esi, %ecx
[-,%rcx] v40 = bor v1, v2 ; bin: 40 09 f1
; asm: orl %r10d, %esi
[-,%rsi] v41 = bor v2, v3 ; bin: 44 09 d6
; asm: orl %ecx, %r10d
[-,%r10] v42 = bor v3, v1 ; bin: 41 09 ca
; asm: xorl %esi, %ecx
[-,%rcx] v50 = bxor v1, v2 ; bin: 40 31 f1
; asm: xorl %r10d, %esi
[-,%rsi] v51 = bxor v2, v3 ; bin: 44 31 d6
; asm: xorl %ecx, %r10d
[-,%r10] v52 = bxor v3, v1 ; bin: 41 31 ca
; asm: movl %esi, %ecx
[-,%rcx] v60 = copy v2 ; bin: 40 89 f1
; asm: movl %r10d, %esi
[-,%rsi] v61 = copy v3 ; bin: 44 89 d6
; asm: movl %ecx, %r10d
[-,%r10] v62 = copy v1 ; bin: 41 89 ca
; Integer Register-Immediate Operations.
; These 64-bit ops all use a 32-bit immediate that is sign-extended to 64 bits.
; Some take 8-bit immediates that are sign-extended to 64 bits.
; asm: addl $-100000, %ecx
[-,%rcx] v70 = iadd_imm v1, -100000 ; bin: 40 81 c1 fffe7960
; asm: addl $100000, %esi
[-,%rsi] v71 = iadd_imm v2, 100000 ; bin: 40 81 c6 000186a0
; asm: addl $0x7fffffff, %r10d
[-,%r10] v72 = iadd_imm v3, 0x7fff_ffff ; bin: 41 81 c2 7fffffff
; asm: addl $100, %r8d
[-,%r8] v73 = iadd_imm v4, 100 ; bin: 41 83 c0 64
; asm: addl $-100, %r14d
[-,%r14] v74 = iadd_imm v5, -100 ; bin: 41 83 c6 9c
; asm: andl $-100000, %ecx
[-,%rcx] v80 = band_imm v1, -100000 ; bin: 40 81 e1 fffe7960
; asm: andl $100000, %esi
[-,%rsi] v81 = band_imm v2, 100000 ; bin: 40 81 e6 000186a0
; asm: andl $0x7fffffff, %r10d
[-,%r10] v82 = band_imm v3, 0x7fff_ffff ; bin: 41 81 e2 7fffffff
; asm: andl $100, %r8d
[-,%r8] v83 = band_imm v4, 100 ; bin: 41 83 e0 64
; asm: andl $-100, %r14d
[-,%r14] v84 = band_imm v5, -100 ; bin: 41 83 e6 9c
; asm: orl $-100000, %ecx
[-,%rcx] v90 = bor_imm v1, -100000 ; bin: 40 81 c9 fffe7960
; asm: orl $100000, %esi
[-,%rsi] v91 = bor_imm v2, 100000 ; bin: 40 81 ce 000186a0
; asm: orl $0x7fffffff, %r10d
[-,%r10] v92 = bor_imm v3, 0x7fff_ffff ; bin: 41 81 ca 7fffffff
; asm: orl $100, %r8d
[-,%r8] v93 = bor_imm v4, 100 ; bin: 41 83 c8 64
; asm: orl $-100, %r14d
[-,%r14] v94 = bor_imm v5, -100 ; bin: 41 83 ce 9c
; asm: ret
; asm: xorl $-100000, %ecx
[-,%rcx] v100 = bxor_imm v1, -100000 ; bin: 40 81 f1 fffe7960
; asm: xorl $100000, %esi
[-,%rsi] v101 = bxor_imm v2, 100000 ; bin: 40 81 f6 000186a0
; asm: xorl $0x7fffffff, %r10d
[-,%r10] v102 = bxor_imm v3, 0x7fff_ffff ; bin: 41 81 f2 7fffffff
; asm: xorl $100, %r8d
[-,%r8] v103 = bxor_imm v4, 100 ; bin: 41 83 f0 64
; asm: xorl $-100, %r14d
[-,%r14] v104 = bxor_imm v5, -100 ; bin: 41 83 f6 9c
return ; bin: c3
}