Add x86-specific shuffle instructions
This includes both PSHUFD and PSHUFB; these are necessary to legalize future SIMD instructions.
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@@ -7,7 +7,7 @@ use crate::cdsl::instructions::{
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use crate::cdsl::operands::{create_operand as operand, create_operand_doc as operand_doc};
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use crate::cdsl::types::ValueType;
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use crate::cdsl::typevar::{Interval, TypeSetBuilder, TypeVar};
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use crate::shared::types;
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use crate::shared::{immediates, types, OperandKinds};
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pub fn define(
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mut all_instructions: &mut AllInstructions,
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@@ -249,5 +249,46 @@ pub fn define(
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.operands_out(vec![y, rflags]),
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);
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let immediates = OperandKinds::from(immediates::define());
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let uimm8 = immediates.by_name("uimm8");
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let TxN = &TypeVar::new(
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"TxN",
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"A SIMD vector type",
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TypeSetBuilder::new()
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.ints(Interval::All)
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.floats(Interval::All)
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.bools(Interval::All)
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.simd_lanes(Interval::All)
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.includes_scalars(false)
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.build(),
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);
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let a = &operand_doc("a", TxN, "A vector value (i.e. held in an XMM register)");
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let b = &operand_doc("b", TxN, "A vector value (i.e. held in an XMM register)");
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let i = &operand_doc("i", uimm8, "An ordering operand controlling the copying of data from the source to the destination; see PSHUFD in Intel manual for details");
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ig.push(
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Inst::new(
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"x86_pshufd",
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r#"
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Packed Shuffle Doublewords -- copies data from either memory or lanes in an extended
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register and re-orders the data according to the passed immediate byte.
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"#,
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)
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.operands_in(vec![a, i]) // TODO allow copying from memory here (need more permissive type than TxN)
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.operands_out(vec![a]),
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);
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ig.push(
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Inst::new(
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"x86_pshufb",
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r#"
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Packed Shuffle Bytes -- re-orders data in an extended register using a shuffle
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mask from either memory or another extended register
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"#,
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)
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.operands_in(vec![a, b]) // TODO allow re-ordering from memory here (need more permissive type than TxN)
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.operands_out(vec![a]),
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);
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ig.build()
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}
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