From 682ef7b47088e9f2127e98b56a2448fae9fc5920 Mon Sep 17 00:00:00 2001 From: Sam Parker Date: Thu, 14 Apr 2022 22:51:12 +0100 Subject: [PATCH] [AArch64] Refactor Mov instructions (#4033) Merge Mov32 and Mov64 into a single instruction parameterized by a new OperandSize field. Also combine the Mov[K,N,Z] into a single instruction with a new opcode to select between the operations. Copyright (c) 2022, Arm Limited. --- cranelift/codegen/src/isa/aarch64/inst.isle | 44 +-- .../codegen/src/isa/aarch64/inst/emit.rs | 103 +++--- .../src/isa/aarch64/inst/emit_tests.rs | 54 ++- cranelift/codegen/src/isa/aarch64/inst/mod.rs | 91 +++-- .../codegen/src/isa/aarch64/lower/isle.rs | 26 +- .../lower/isle/generated_code.manifest | 2 +- .../isa/aarch64/lower/isle/generated_code.rs | 348 +++++++++--------- 7 files changed, 349 insertions(+), 319 deletions(-) diff --git a/cranelift/codegen/src/isa/aarch64/inst.isle b/cranelift/codegen/src/isa/aarch64/inst.isle index c589ab0db5..722ef38889 100644 --- a/cranelift/codegen/src/isa/aarch64/inst.isle +++ b/cranelift/codegen/src/isa/aarch64/inst.isle @@ -156,33 +156,18 @@ (mem PairAMode) (flags MemFlags)) - ;; A MOV instruction. These are encoded as ORR's (AluRRR form) but we - ;; keep them separate at the `Inst` level for better pretty-printing - ;; and faster `is_move()` logic. - (Mov64 + ;; A MOV instruction. These are encoded as ORR's (AluRRR form). + ;; The 32-bit version zeroes the top 32 bits of the + ;; destination, which is effectively an alias for an unsigned + ;; 32-to-64-bit extension. + (Mov + (size OperandSize) (rd WritableReg) (rm Reg)) - ;; A 32-bit MOV. Zeroes the top 32 bits of the destination. This is - ;; effectively an alias for an unsigned 32-to-64-bit extension. - (Mov32 - (rd WritableReg) - (rm Reg)) - - ;; A MOVZ with a 16-bit immediate. - (MovZ - (rd WritableReg) - (imm MoveWideConst) - (size OperandSize)) - - ;; A MOVN with a 16-bit immediate. - (MovN - (rd WritableReg) - (imm MoveWideConst) - (size OperandSize)) - - ;; A MOVK with a 16-bit immediate. - (MovK + ;; A MOV[Z,N,K] with a 16-bit immediate. + (MovWide + (op MoveWideOp) (rd WritableReg) (imm MoveWideConst) (size OperandSize)) @@ -841,6 +826,13 @@ (MSub) )) +(type MoveWideOp + (enum + (MovZ) + (MovN) + (MovK) +)) + (type UImm5 (primitive UImm5)) (type Imm12 (primitive Imm12)) (type ImmLogic (primitive ImmLogic)) @@ -1361,14 +1353,14 @@ (decl movz (MoveWideConst OperandSize) Reg) (rule (movz imm size) (let ((dst WritableReg (temp_writable_reg $I64)) - (_ Unit (emit (MInst.MovZ dst imm size)))) + (_ Unit (emit (MInst.MovWide (MoveWideOp.MovZ) dst imm size)))) dst)) ;; Helper for emitting `MInst.MovN` instructions. (decl movn (MoveWideConst OperandSize) Reg) (rule (movn imm size) (let ((dst WritableReg (temp_writable_reg $I64)) - (_ Unit (emit (MInst.MovN dst imm size)))) + (_ Unit (emit (MInst.MovWide (MoveWideOp.MovN) dst imm size)))) dst)) ;; Helper for emitting `MInst.AluRRImmLogic` instructions. diff --git a/cranelift/codegen/src/isa/aarch64/inst/emit.rs b/cranelift/codegen/src/isa/aarch64/inst/emit.rs index f09229c98b..79e7c3a68e 100644 --- a/cranelift/codegen/src/isa/aarch64/inst/emit.rs +++ b/cranelift/codegen/src/isa/aarch64/inst/emit.rs @@ -185,25 +185,16 @@ fn enc_conditional_br( } } -const MOVE_WIDE_FIXED: u32 = 0x12800000; - -#[repr(u32)] -enum MoveWideOpcode { - MOVN = 0b00, - MOVZ = 0b10, - MOVK = 0b11, -} - -fn enc_move_wide( - op: MoveWideOpcode, - rd: Writable, - imm: MoveWideConst, - size: OperandSize, -) -> u32 { +fn enc_move_wide(op: MoveWideOp, rd: Writable, imm: MoveWideConst, size: OperandSize) -> u32 { assert!(imm.shift <= 0b11); - MOVE_WIDE_FIXED + let op = match op { + MoveWideOp::MovN => 0b00, + MoveWideOp::MovZ => 0b10, + MoveWideOp::MovK => 0b11, + }; + 0x12800000 | size.sf_bit() << 31 - | (op as u32) << 29 + | op << 29 | u32::from(imm.shift) << 21 | u32::from(imm.bits) << 5 | machreg_to_gpr(rd.to_reg()) @@ -1315,51 +1306,45 @@ impl MachInstEmit for Inst { } } } - &Inst::Mov64 { rd, rm } => { + &Inst::Mov { size, rd, rm } => { let rd = allocs.next_writable(rd); let rm = allocs.next(rm); assert!(rd.to_reg().class() == rm.class()); assert!(rm.class() == RegClass::Int); - // MOV to SP is interpreted as MOV to XZR instead. And our codegen - // should never MOV to XZR. - assert!(rd.to_reg() != stack_reg()); + match size { + OperandSize::Size64 => { + // MOV to SP is interpreted as MOV to XZR instead. And our codegen + // should never MOV to XZR. + assert!(rd.to_reg() != stack_reg()); - if rm == stack_reg() { - // We can't use ORR here, so use an `add rd, sp, #0` instead. - let imm12 = Imm12::maybe_from_u64(0).unwrap(); - sink.put4(enc_arith_rr_imm12( - 0b100_10001, - imm12.shift_bits(), - imm12.imm_bits(), - rm, - rd, - )); - } else { - // Encoded as ORR rd, rm, zero. - sink.put4(enc_arith_rrr(0b10101010_000, 0b000_000, rd, zero_reg(), rm)); + if rm == stack_reg() { + // We can't use ORR here, so use an `add rd, sp, #0` instead. + let imm12 = Imm12::maybe_from_u64(0).unwrap(); + sink.put4(enc_arith_rr_imm12( + 0b100_10001, + imm12.shift_bits(), + imm12.imm_bits(), + rm, + rd, + )); + } else { + // Encoded as ORR rd, rm, zero. + sink.put4(enc_arith_rrr(0b10101010_000, 0b000_000, rd, zero_reg(), rm)); + } + } + OperandSize::Size32 => { + // MOV to SP is interpreted as MOV to XZR instead. And our codegen + // should never MOV to XZR. + assert!(machreg_to_gpr(rd.to_reg()) != 31); + // Encoded as ORR rd, rm, zero. + sink.put4(enc_arith_rrr(0b00101010_000, 0b000_000, rd, zero_reg(), rm)); + } } } - &Inst::Mov32 { rd, rm } => { + &Inst::MovWide { op, rd, imm, size } => { let rd = allocs.next_writable(rd); - let rm = allocs.next(rm); - // MOV to SP is interpreted as MOV to XZR instead. And our codegen - // should never MOV to XZR. - assert!(machreg_to_gpr(rd.to_reg()) != 31); - // Encoded as ORR rd, rm, zero. - sink.put4(enc_arith_rrr(0b00101010_000, 0b000_000, rd, zero_reg(), rm)); - } - &Inst::MovZ { rd, imm, size } => { - let rd = allocs.next_writable(rd); - sink.put4(enc_move_wide(MoveWideOpcode::MOVZ, rd, imm, size)) - } - &Inst::MovN { rd, imm, size } => { - let rd = allocs.next_writable(rd); - sink.put4(enc_move_wide(MoveWideOpcode::MOVN, rd, imm, size)) - } - &Inst::MovK { rd, imm, size } => { - let rd = allocs.next_writable(rd); - sink.put4(enc_move_wide(MoveWideOpcode::MOVK, rd, imm, size)) + sink.put4(enc_move_wide(op, rd, imm, size)); } &Inst::CSel { rd, rn, rm, cond } => { let rd = allocs.next_writable(rd); @@ -2700,7 +2685,11 @@ impl MachInstEmit for Inst { } => { let rd = allocs.next_writable(rd); let rn = allocs.next(rn); - let mov = Inst::Mov32 { rd, rm: rn }; + let mov = Inst::Mov { + size: OperandSize::Size32, + rd, + rm: rn, + }; mov.emit(&[], sink, emit_info, state); } &Inst::Extend { @@ -2980,7 +2969,11 @@ impl MachInstEmit for Inst { add.emit(&[], sink, emit_info, state); } else if offset == 0 { if reg != rd.to_reg() { - let mov = Inst::Mov64 { rd, rm: reg }; + let mov = Inst::Mov { + size: OperandSize::Size64, + rd, + rm: reg, + }; mov.emit(&[], sink, emit_info, state); } diff --git a/cranelift/codegen/src/isa/aarch64/inst/emit_tests.rs b/cranelift/codegen/src/isa/aarch64/inst/emit_tests.rs index 0ca568dddd..62d3c5295c 100644 --- a/cranelift/codegen/src/isa/aarch64/inst/emit_tests.rs +++ b/cranelift/codegen/src/isa/aarch64/inst/emit_tests.rs @@ -1920,7 +1920,8 @@ fn test_aarch64_binemit() { )); insns.push(( - Inst::Mov64 { + Inst::Mov { + size: OperandSize::Size64, rd: writable_xreg(8), rm: xreg(9), }, @@ -1928,7 +1929,8 @@ fn test_aarch64_binemit() { "mov x8, x9", )); insns.push(( - Inst::Mov32 { + Inst::Mov { + size: OperandSize::Size32, rd: writable_xreg(8), rm: xreg(9), }, @@ -1937,7 +1939,8 @@ fn test_aarch64_binemit() { )); insns.push(( - Inst::MovZ { + Inst::MovWide { + op: MoveWideOp::MovZ, rd: writable_xreg(8), imm: MoveWideConst::maybe_from_u64(0x0000_0000_0000_ffff).unwrap(), size: OperandSize::Size64, @@ -1946,7 +1949,8 @@ fn test_aarch64_binemit() { "movz x8, #65535", )); insns.push(( - Inst::MovZ { + Inst::MovWide { + op: MoveWideOp::MovZ, rd: writable_xreg(8), imm: MoveWideConst::maybe_from_u64(0x0000_0000_ffff_0000).unwrap(), size: OperandSize::Size64, @@ -1955,7 +1959,8 @@ fn test_aarch64_binemit() { "movz x8, #65535, LSL #16", )); insns.push(( - Inst::MovZ { + Inst::MovWide { + op: MoveWideOp::MovZ, rd: writable_xreg(8), imm: MoveWideConst::maybe_from_u64(0x0000_ffff_0000_0000).unwrap(), size: OperandSize::Size64, @@ -1964,7 +1969,8 @@ fn test_aarch64_binemit() { "movz x8, #65535, LSL #32", )); insns.push(( - Inst::MovZ { + Inst::MovWide { + op: MoveWideOp::MovZ, rd: writable_xreg(8), imm: MoveWideConst::maybe_from_u64(0xffff_0000_0000_0000).unwrap(), size: OperandSize::Size64, @@ -1973,7 +1979,8 @@ fn test_aarch64_binemit() { "movz x8, #65535, LSL #48", )); insns.push(( - Inst::MovZ { + Inst::MovWide { + op: MoveWideOp::MovZ, rd: writable_xreg(8), imm: MoveWideConst::maybe_from_u64(0x0000_0000_ffff_0000).unwrap(), size: OperandSize::Size32, @@ -1983,7 +1990,8 @@ fn test_aarch64_binemit() { )); insns.push(( - Inst::MovN { + Inst::MovWide { + op: MoveWideOp::MovN, rd: writable_xreg(8), imm: MoveWideConst::maybe_from_u64(0x0000_0000_0000_ffff).unwrap(), size: OperandSize::Size64, @@ -1992,7 +2000,8 @@ fn test_aarch64_binemit() { "movn x8, #65535", )); insns.push(( - Inst::MovN { + Inst::MovWide { + op: MoveWideOp::MovN, rd: writable_xreg(8), imm: MoveWideConst::maybe_from_u64(0x0000_0000_ffff_0000).unwrap(), size: OperandSize::Size64, @@ -2001,7 +2010,8 @@ fn test_aarch64_binemit() { "movn x8, #65535, LSL #16", )); insns.push(( - Inst::MovN { + Inst::MovWide { + op: MoveWideOp::MovN, rd: writable_xreg(8), imm: MoveWideConst::maybe_from_u64(0x0000_ffff_0000_0000).unwrap(), size: OperandSize::Size64, @@ -2010,7 +2020,8 @@ fn test_aarch64_binemit() { "movn x8, #65535, LSL #32", )); insns.push(( - Inst::MovN { + Inst::MovWide { + op: MoveWideOp::MovN, rd: writable_xreg(8), imm: MoveWideConst::maybe_from_u64(0xffff_0000_0000_0000).unwrap(), size: OperandSize::Size64, @@ -2019,7 +2030,8 @@ fn test_aarch64_binemit() { "movn x8, #65535, LSL #48", )); insns.push(( - Inst::MovN { + Inst::MovWide { + op: MoveWideOp::MovN, rd: writable_xreg(8), imm: MoveWideConst::maybe_from_u64(0x0000_0000_0000_ffff).unwrap(), size: OperandSize::Size32, @@ -2029,7 +2041,8 @@ fn test_aarch64_binemit() { )); insns.push(( - Inst::MovK { + Inst::MovWide { + op: MoveWideOp::MovK, rd: writable_xreg(12), imm: MoveWideConst::maybe_from_u64(0x0000_0000_0000_0000).unwrap(), size: OperandSize::Size64, @@ -2038,7 +2051,8 @@ fn test_aarch64_binemit() { "movk x12, #0", )); insns.push(( - Inst::MovK { + Inst::MovWide { + op: MoveWideOp::MovK, rd: writable_xreg(19), imm: MoveWideConst::maybe_with_shift(0x0000, 16).unwrap(), size: OperandSize::Size64, @@ -2047,7 +2061,8 @@ fn test_aarch64_binemit() { "movk x19, #0, LSL #16", )); insns.push(( - Inst::MovK { + Inst::MovWide { + op: MoveWideOp::MovK, rd: writable_xreg(3), imm: MoveWideConst::maybe_from_u64(0x0000_0000_0000_ffff).unwrap(), size: OperandSize::Size64, @@ -2056,7 +2071,8 @@ fn test_aarch64_binemit() { "movk x3, #65535", )); insns.push(( - Inst::MovK { + Inst::MovWide { + op: MoveWideOp::MovK, rd: writable_xreg(8), imm: MoveWideConst::maybe_from_u64(0x0000_0000_ffff_0000).unwrap(), size: OperandSize::Size64, @@ -2065,7 +2081,8 @@ fn test_aarch64_binemit() { "movk x8, #65535, LSL #16", )); insns.push(( - Inst::MovK { + Inst::MovWide { + op: MoveWideOp::MovK, rd: writable_xreg(8), imm: MoveWideConst::maybe_from_u64(0x0000_ffff_0000_0000).unwrap(), size: OperandSize::Size64, @@ -2074,7 +2091,8 @@ fn test_aarch64_binemit() { "movk x8, #65535, LSL #32", )); insns.push(( - Inst::MovK { + Inst::MovWide { + op: MoveWideOp::MovK, rd: writable_xreg(8), imm: MoveWideConst::maybe_from_u64(0xffff_0000_0000_0000).unwrap(), size: OperandSize::Size64, diff --git a/cranelift/codegen/src/isa/aarch64/inst/mod.rs b/cranelift/codegen/src/isa/aarch64/inst/mod.rs index 46c76b08b0..9dbcec49ab 100644 --- a/cranelift/codegen/src/isa/aarch64/inst/mod.rs +++ b/cranelift/codegen/src/isa/aarch64/inst/mod.rs @@ -40,8 +40,8 @@ mod emit_tests; pub use crate::isa::aarch64::lower::isle::generated_code::{ ALUOp, ALUOp3, AtomicRMWOp, BitOp, FPUOp1, FPUOp2, FPUOp3, FpuRoundMode, FpuToIntOp, - IntToFpuOp, MInst as Inst, VecALUOp, VecExtendOp, VecLanesOp, VecMisc2, VecPairOp, VecRRLongOp, - VecRRNarrowOp, VecRRPairLongOp, VecRRRLongOp, VecShiftImmOp, + IntToFpuOp, MInst as Inst, MoveWideOp, VecALUOp, VecExtendOp, VecLanesOp, VecMisc2, VecPairOp, + VecRRLongOp, VecRRNarrowOp, VecRRPairLongOp, VecRRRLongOp, VecShiftImmOp, }; /// A floating-point unit (FPU) operation with two args, a register and an immediate. @@ -130,14 +130,16 @@ impl Inst { if let Some(imm) = MoveWideConst::maybe_from_u64(value) { // 16-bit immediate (shifted by 0, 16, 32 or 48 bits) in MOVZ - smallvec![Inst::MovZ { + smallvec![Inst::MovWide { + op: MoveWideOp::MovZ, rd, imm, size: OperandSize::Size64 }] } else if let Some(imm) = MoveWideConst::maybe_from_u64(!value) { // 16-bit immediate (shifted by 0, 16, 32 or 48 bits) in MOVN - smallvec![Inst::MovN { + smallvec![Inst::MovWide { + op: MoveWideOp::MovN, rd, imm, size: OperandSize::Size64 @@ -178,15 +180,30 @@ impl Inst { let imm = MoveWideConst::maybe_with_shift(((!imm16) & 0xffff) as u16, i * 16) .unwrap(); - insts.push(Inst::MovN { rd, imm, size }); + insts.push(Inst::MovWide { + op: MoveWideOp::MovN, + rd, + imm, + size, + }); } else { let imm = MoveWideConst::maybe_with_shift(imm16 as u16, i * 16).unwrap(); - insts.push(Inst::MovZ { rd, imm, size }); + insts.push(Inst::MovWide { + op: MoveWideOp::MovZ, + rd, + imm, + size, + }); } } else { let imm = MoveWideConst::maybe_with_shift(imm16 as u16, i * 16).unwrap(); - insts.push(Inst::MovK { rd, imm, size }); + insts.push(Inst::MovWide { + op: MoveWideOp::MovK, + rd, + imm, + size, + }); } } } @@ -641,20 +658,14 @@ fn aarch64_get_operands VReg>(inst: &Inst, collector: &mut Operan collector.reg_def(rt2); pairmemarg_operands(mem, collector); } - &Inst::Mov64 { rd, rm } => { + &Inst::Mov { rd, rm, .. } => { collector.reg_def(rd); collector.reg_use(rm); } - &Inst::Mov32 { rd, rm } => { - collector.reg_def(rd); - collector.reg_use(rm); - } - &Inst::MovZ { rd, .. } | &Inst::MovN { rd, .. } => { - collector.reg_def(rd); - } - &Inst::MovK { rd, .. } => { - collector.reg_mod(rd); - } + &Inst::MovWide { op, rd, .. } => match op { + MoveWideOp::MovK => collector.reg_mod(rd), + _ => collector.reg_def(rd), + }, &Inst::CSel { rd, rn, rm, .. } => { collector.reg_def(rd); collector.reg_use(rn); @@ -1043,7 +1054,11 @@ impl MachInst for Inst { fn is_move(&self) -> Option<(Writable, Reg)> { match self { - &Inst::Mov64 { rd, rm } => Some((rd, rm)), + &Inst::Mov { + size: OperandSize::Size64, + rd, + rm, + } => Some((rd, rm)), &Inst::FpuMove64 { rd, rn } => Some((rd, rn)), &Inst::FpuMove128 { rd, rn } => Some((rd, rn)), _ => None, @@ -1097,7 +1112,8 @@ impl MachInst for Inst { assert!(bits <= 128); assert!(to_reg.to_reg().class() == from_reg.class()); match from_reg.class() { - RegClass::Int => Inst::Mov64 { + RegClass::Int => Inst::Mov { + size: OperandSize::Size64, rd: to_reg, rm: from_reg, }, @@ -1467,30 +1483,25 @@ impl Inst { let mem = mem.pretty_print_default(); format!("ldp {}, {}, {}", rt, rt2, mem) } - &Inst::Mov64 { rd, rm } => { - let rd = pretty_print_ireg(rd.to_reg(), OperandSize::Size64, allocs); - let rm = pretty_print_ireg(rm, OperandSize::Size64, allocs); + &Inst::Mov { size, rd, rm } => { + let rd = pretty_print_ireg(rd.to_reg(), size, allocs); + let rm = pretty_print_ireg(rm, size, allocs); format!("mov {}, {}", rd, rm) } - &Inst::Mov32 { rd, rm } => { - let rd = pretty_print_ireg(rd.to_reg(), OperandSize::Size32, allocs); - let rm = pretty_print_ireg(rm, OperandSize::Size32, allocs); - format!("mov {}, {}", rd, rm) - } - &Inst::MovZ { rd, ref imm, size } => { + &Inst::MovWide { + op, + rd, + ref imm, + size, + } => { + let op_str = match op { + MoveWideOp::MovZ => "movz", + MoveWideOp::MovN => "movn", + MoveWideOp::MovK => "movk", + }; let rd = pretty_print_ireg(rd.to_reg(), size, allocs); let imm = imm.pretty_print(0, allocs); - format!("movz {}, {}", rd, imm) - } - &Inst::MovN { rd, ref imm, size } => { - let rd = pretty_print_ireg(rd.to_reg(), size, allocs); - let imm = imm.pretty_print(0, allocs); - format!("movn {}, {}", rd, imm) - } - &Inst::MovK { rd, ref imm, size } => { - let rd = pretty_print_ireg(rd.to_reg(), size, allocs); - let imm = imm.pretty_print(0, allocs); - format!("movk {}, {}", rd, imm) + format!("{} {}, {}", op_str, rd, imm) } &Inst::CSel { rd, rn, rm, cond } => { let rd = pretty_print_ireg(rd.to_reg(), OperandSize::Size64, allocs); diff --git a/cranelift/codegen/src/isa/aarch64/lower/isle.rs b/cranelift/codegen/src/isa/aarch64/lower/isle.rs index da397aa660..7dda0dac37 100644 --- a/cranelift/codegen/src/isa/aarch64/lower/isle.rs +++ b/cranelift/codegen/src/isa/aarch64/lower/isle.rs @@ -7,8 +7,9 @@ pub mod generated_code; use super::{ writable_zero_reg, zero_reg, AMode, ASIMDFPModImm, ASIMDMovModImm, AtomicRmwOp, BranchTarget, CallIndInfo, CallInfo, Cond, CondBrKind, ExtendOp, FPUOpRI, FloatCC, Imm12, ImmLogic, ImmShift, - Inst as MInst, IntCC, JTSequenceInfo, MachLabel, MoveWideConst, NarrowValueMode, Opcode, - OperandSize, PairAMode, Reg, ScalarSize, ShiftOpAndAmt, UImm5, VecMisc2, VectorSize, NZCV, + Inst as MInst, IntCC, JTSequenceInfo, MachLabel, MoveWideConst, MoveWideOp, NarrowValueMode, + Opcode, OperandSize, PairAMode, Reg, ScalarSize, ShiftOpAndAmt, UImm5, VecMisc2, VectorSize, + NZCV, }; use crate::isa::aarch64::settings::Flags as IsaFlags; use crate::machinst::isle::*; @@ -145,14 +146,29 @@ where let imm = MoveWideConst::maybe_with_shift(((!imm16) & 0xffff) as u16, i * 16) .unwrap(); - self.emit(&MInst::MovN { rd, imm, size }); + self.emit(&MInst::MovWide { + op: MoveWideOp::MovN, + rd, + imm, + size, + }); } else { let imm = MoveWideConst::maybe_with_shift(imm16 as u16, i * 16).unwrap(); - self.emit(&MInst::MovZ { rd, imm, size }); + self.emit(&MInst::MovWide { + op: MoveWideOp::MovZ, + rd, + imm, + size, + }); } } else { let imm = MoveWideConst::maybe_with_shift(imm16 as u16, i * 16).unwrap(); - self.emit(&MInst::MovK { rd, imm, size }); + self.emit(&MInst::MovWide { + op: MoveWideOp::MovK, + rd, + imm, + size, + }); } } } diff --git a/cranelift/codegen/src/isa/aarch64/lower/isle/generated_code.manifest b/cranelift/codegen/src/isa/aarch64/lower/isle/generated_code.manifest index c35834b9f3..63e2135f7d 100644 --- a/cranelift/codegen/src/isa/aarch64/lower/isle/generated_code.manifest +++ b/cranelift/codegen/src/isa/aarch64/lower/isle/generated_code.manifest @@ -1,4 +1,4 @@ src/clif.isle 443b34b797fc8ace src/prelude.isle afd037c4d91c875c -src/isa/aarch64/inst.isle 950bb0092242218e +src/isa/aarch64/inst.isle f7f03d5ea5411344 src/isa/aarch64/lower.isle 71c7e603b0e4bdef diff --git a/cranelift/codegen/src/isa/aarch64/lower/isle/generated_code.rs b/cranelift/codegen/src/isa/aarch64/lower/isle/generated_code.rs index 5b00b2e408..055fdecda7 100644 --- a/cranelift/codegen/src/isa/aarch64/lower/isle/generated_code.rs +++ b/cranelift/codegen/src/isa/aarch64/lower/isle/generated_code.rs @@ -300,25 +300,13 @@ pub enum MInst { mem: PairAMode, flags: MemFlags, }, - Mov64 { + Mov { + size: OperandSize, rd: WritableReg, rm: Reg, }, - Mov32 { - rd: WritableReg, - rm: Reg, - }, - MovZ { - rd: WritableReg, - imm: MoveWideConst, - size: OperandSize, - }, - MovN { - rd: WritableReg, - imm: MoveWideConst, - size: OperandSize, - }, - MovK { + MovWide { + op: MoveWideOp, rd: WritableReg, imm: MoveWideConst, size: OperandSize, @@ -749,7 +737,7 @@ pub enum MInst { }, } -/// Internal type ALUOp: defined at src/isa/aarch64/inst.isle line 798. +/// Internal type ALUOp: defined at src/isa/aarch64/inst.isle line 783. #[derive(Copy, Clone, PartialEq, Eq, Debug)] pub enum ALUOp { Add, @@ -777,14 +765,22 @@ pub enum ALUOp { SbcS, } -/// Internal type ALUOp3: defined at src/isa/aarch64/inst.isle line 836. +/// Internal type ALUOp3: defined at src/isa/aarch64/inst.isle line 821. #[derive(Copy, Clone, PartialEq, Eq, Debug)] pub enum ALUOp3 { MAdd, MSub, } -/// Internal type BitOp: defined at src/isa/aarch64/inst.isle line 875. +/// Internal type MoveWideOp: defined at src/isa/aarch64/inst.isle line 829. +#[derive(Copy, Clone, PartialEq, Eq, Debug)] +pub enum MoveWideOp { + MovZ, + MovN, + MovK, +} + +/// Internal type BitOp: defined at src/isa/aarch64/inst.isle line 867. #[derive(Copy, Clone, PartialEq, Eq, Debug)] pub enum BitOp { RBit, @@ -792,7 +788,7 @@ pub enum BitOp { Cls, } -/// Internal type FPUOp1: defined at src/isa/aarch64/inst.isle line 942. +/// Internal type FPUOp1: defined at src/isa/aarch64/inst.isle line 934. #[derive(Copy, Clone, PartialEq, Eq, Debug)] pub enum FPUOp1 { Abs, @@ -802,7 +798,7 @@ pub enum FPUOp1 { Cvt64To32, } -/// Internal type FPUOp2: defined at src/isa/aarch64/inst.isle line 952. +/// Internal type FPUOp2: defined at src/isa/aarch64/inst.isle line 944. #[derive(Copy, Clone, PartialEq, Eq, Debug)] pub enum FPUOp2 { Add, @@ -813,14 +809,14 @@ pub enum FPUOp2 { Min, } -/// Internal type FPUOp3: defined at src/isa/aarch64/inst.isle line 963. +/// Internal type FPUOp3: defined at src/isa/aarch64/inst.isle line 955. #[derive(Copy, Clone, PartialEq, Eq, Debug)] pub enum FPUOp3 { MAdd32, MAdd64, } -/// Internal type FpuToIntOp: defined at src/isa/aarch64/inst.isle line 970. +/// Internal type FpuToIntOp: defined at src/isa/aarch64/inst.isle line 962. #[derive(Copy, Clone, PartialEq, Eq, Debug)] pub enum FpuToIntOp { F32ToU32, @@ -833,7 +829,7 @@ pub enum FpuToIntOp { F64ToI64, } -/// Internal type IntToFpuOp: defined at src/isa/aarch64/inst.isle line 983. +/// Internal type IntToFpuOp: defined at src/isa/aarch64/inst.isle line 975. #[derive(Copy, Clone, PartialEq, Eq, Debug)] pub enum IntToFpuOp { U32ToF32, @@ -846,7 +842,7 @@ pub enum IntToFpuOp { I64ToF64, } -/// Internal type FpuRoundMode: defined at src/isa/aarch64/inst.isle line 997. +/// Internal type FpuRoundMode: defined at src/isa/aarch64/inst.isle line 989. #[derive(Copy, Clone, PartialEq, Eq, Debug)] pub enum FpuRoundMode { Minus32, @@ -859,7 +855,7 @@ pub enum FpuRoundMode { Nearest64, } -/// Internal type VecExtendOp: defined at src/isa/aarch64/inst.isle line 1010. +/// Internal type VecExtendOp: defined at src/isa/aarch64/inst.isle line 1002. #[derive(Copy, Clone, PartialEq, Eq, Debug)] pub enum VecExtendOp { Sxtl8, @@ -870,7 +866,7 @@ pub enum VecExtendOp { Uxtl32, } -/// Internal type VecALUOp: defined at src/isa/aarch64/inst.isle line 1027. +/// Internal type VecALUOp: defined at src/isa/aarch64/inst.isle line 1019. #[derive(Copy, Clone, PartialEq, Eq, Debug)] pub enum VecALUOp { Sqadd, @@ -912,7 +908,7 @@ pub enum VecALUOp { Sqrdmulh, } -/// Internal type VecMisc2: defined at src/isa/aarch64/inst.isle line 1106. +/// Internal type VecMisc2: defined at src/isa/aarch64/inst.isle line 1098. #[derive(Copy, Clone, PartialEq, Eq, Debug)] pub enum VecMisc2 { Not, @@ -943,7 +939,7 @@ pub enum VecMisc2 { Fcmlt0, } -/// Internal type VecRRLongOp: defined at src/isa/aarch64/inst.isle line 1163. +/// Internal type VecRRLongOp: defined at src/isa/aarch64/inst.isle line 1155. #[derive(Copy, Clone, PartialEq, Eq, Debug)] pub enum VecRRLongOp { Fcvtl16, @@ -953,7 +949,7 @@ pub enum VecRRLongOp { Shll32, } -/// Internal type VecRRNarrowOp: defined at src/isa/aarch64/inst.isle line 1178. +/// Internal type VecRRNarrowOp: defined at src/isa/aarch64/inst.isle line 1170. #[derive(Copy, Clone, PartialEq, Eq, Debug)] pub enum VecRRNarrowOp { Xtn16, @@ -972,7 +968,7 @@ pub enum VecRRNarrowOp { Fcvtn64, } -/// Internal type VecRRRLongOp: defined at src/isa/aarch64/inst.isle line 1210. +/// Internal type VecRRRLongOp: defined at src/isa/aarch64/inst.isle line 1202. #[derive(Copy, Clone, PartialEq, Eq, Debug)] pub enum VecRRRLongOp { Smull8, @@ -986,13 +982,13 @@ pub enum VecRRRLongOp { Umlal32, } -/// Internal type VecPairOp: defined at src/isa/aarch64/inst.isle line 1227. +/// Internal type VecPairOp: defined at src/isa/aarch64/inst.isle line 1219. #[derive(Copy, Clone, PartialEq, Eq, Debug)] pub enum VecPairOp { Addp, } -/// Internal type VecRRPairLongOp: defined at src/isa/aarch64/inst.isle line 1235. +/// Internal type VecRRPairLongOp: defined at src/isa/aarch64/inst.isle line 1227. #[derive(Copy, Clone, PartialEq, Eq, Debug)] pub enum VecRRPairLongOp { Saddlp8, @@ -1001,14 +997,14 @@ pub enum VecRRPairLongOp { Uaddlp16, } -/// Internal type VecLanesOp: defined at src/isa/aarch64/inst.isle line 1246. +/// Internal type VecLanesOp: defined at src/isa/aarch64/inst.isle line 1238. #[derive(Copy, Clone, PartialEq, Eq, Debug)] pub enum VecLanesOp { Addv, Uminv, } -/// Internal type VecShiftImmOp: defined at src/isa/aarch64/inst.isle line 1255. +/// Internal type VecShiftImmOp: defined at src/isa/aarch64/inst.isle line 1247. #[derive(Copy, Clone, PartialEq, Eq, Debug)] pub enum VecShiftImmOp { Shl, @@ -1016,7 +1012,7 @@ pub enum VecShiftImmOp { Sshr, } -/// Internal type AtomicRMWOp: defined at src/isa/aarch64/inst.isle line 1266. +/// Internal type AtomicRMWOp: defined at src/isa/aarch64/inst.isle line 1258. #[derive(Copy, Clone, PartialEq, Eq, Debug)] pub enum AtomicRMWOp { Add, @@ -1257,12 +1253,12 @@ pub fn constructor_with_flags_reg( pub fn constructor_operand_size(ctx: &mut C, arg0: Type) -> Option { let pattern0_0 = arg0; if let Some(pattern1_0) = C::fits_in_32(ctx, pattern0_0) { - // Rule at src/isa/aarch64/inst.isle line 893. + // Rule at src/isa/aarch64/inst.isle line 885. let expr0_0 = OperandSize::Size32; return Some(expr0_0); } if let Some(pattern1_0) = C::fits_in_64(ctx, pattern0_0) { - // Rule at src/isa/aarch64/inst.isle line 894. + // Rule at src/isa/aarch64/inst.isle line 886. let expr0_0 = OperandSize::Size64; return Some(expr0_0); } @@ -1275,28 +1271,28 @@ pub fn constructor_vector_size(ctx: &mut C, arg0: Type) -> Option( ) -> Option { let pattern0_0 = arg0; let pattern1_0 = arg1; - // Rule at src/isa/aarch64/inst.isle line 1362. + // Rule at src/isa/aarch64/inst.isle line 1354. let expr0_0: Type = I64; let expr1_0 = C::temp_writable_reg(ctx, expr0_0); - let expr2_0 = MInst::MovZ { + let expr2_0 = MoveWideOp::MovZ; + let expr3_0 = MInst::MovWide { + op: expr2_0, rd: expr1_0, imm: pattern0_0, size: pattern1_0.clone(), }; - let expr3_0 = C::emit(ctx, &expr2_0); - let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0); - return Some(expr4_0); + let expr4_0 = C::emit(ctx, &expr3_0); + let expr5_0 = C::writable_reg_to_reg(ctx, expr1_0); + return Some(expr5_0); } // Generated as internal constructor for term movn. @@ -1334,17 +1332,19 @@ pub fn constructor_movn( ) -> Option { let pattern0_0 = arg0; let pattern1_0 = arg1; - // Rule at src/isa/aarch64/inst.isle line 1369. + // Rule at src/isa/aarch64/inst.isle line 1361. let expr0_0: Type = I64; let expr1_0 = C::temp_writable_reg(ctx, expr0_0); - let expr2_0 = MInst::MovN { + let expr2_0 = MoveWideOp::MovN; + let expr3_0 = MInst::MovWide { + op: expr2_0, rd: expr1_0, imm: pattern0_0, size: pattern1_0.clone(), }; - let expr3_0 = C::emit(ctx, &expr2_0); - let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0); - return Some(expr4_0); + let expr4_0 = C::emit(ctx, &expr3_0); + let expr5_0 = C::writable_reg_to_reg(ctx, expr1_0); + return Some(expr5_0); } // Generated as internal constructor for term alu_rr_imm_logic. @@ -1359,7 +1359,7 @@ pub fn constructor_alu_rr_imm_logic( let pattern1_0 = arg1; let pattern2_0 = arg2; let pattern3_0 = arg3; - // Rule at src/isa/aarch64/inst.isle line 1376. + // Rule at src/isa/aarch64/inst.isle line 1368. let expr0_0: Type = I64; let expr1_0 = C::temp_writable_reg(ctx, expr0_0); let expr2_0 = constructor_operand_size(ctx, pattern1_0)?; @@ -1387,7 +1387,7 @@ pub fn constructor_alu_rr_imm_shift( let pattern1_0 = arg1; let pattern2_0 = arg2; let pattern3_0 = arg3; - // Rule at src/isa/aarch64/inst.isle line 1383. + // Rule at src/isa/aarch64/inst.isle line 1375. let expr0_0: Type = I64; let expr1_0 = C::temp_writable_reg(ctx, expr0_0); let expr2_0 = constructor_operand_size(ctx, pattern1_0)?; @@ -1415,7 +1415,7 @@ pub fn constructor_alu_rrr( let pattern1_0 = arg1; let pattern2_0 = arg2; let pattern3_0 = arg3; - // Rule at src/isa/aarch64/inst.isle line 1390. + // Rule at src/isa/aarch64/inst.isle line 1382. let expr0_0: Type = I64; let expr1_0 = C::temp_writable_reg(ctx, expr0_0); let expr2_0 = constructor_operand_size(ctx, pattern1_0)?; @@ -1443,7 +1443,7 @@ pub fn constructor_vec_rrr( let pattern1_0 = arg1; let pattern2_0 = arg2; let pattern3_0 = arg3; - // Rule at src/isa/aarch64/inst.isle line 1397. + // Rule at src/isa/aarch64/inst.isle line 1389. let expr0_0: Type = I8X16; let expr1_0 = C::temp_writable_reg(ctx, expr0_0); let expr2_0 = MInst::VecRRR { @@ -1468,7 +1468,7 @@ pub fn constructor_vec_lanes( let pattern0_0 = arg0; let pattern1_0 = arg1; let pattern2_0 = arg2; - // Rule at src/isa/aarch64/inst.isle line 1404. + // Rule at src/isa/aarch64/inst.isle line 1396. let expr0_0: Type = I8X16; let expr1_0 = C::temp_writable_reg(ctx, expr0_0); let expr2_0 = MInst::VecLanes { @@ -1486,7 +1486,7 @@ pub fn constructor_vec_lanes( pub fn constructor_vec_dup(ctx: &mut C, arg0: Reg, arg1: &VectorSize) -> Option { let pattern0_0 = arg0; let pattern1_0 = arg1; - // Rule at src/isa/aarch64/inst.isle line 1411. + // Rule at src/isa/aarch64/inst.isle line 1403. let expr0_0: Type = I8X16; let expr1_0 = C::temp_writable_reg(ctx, expr0_0); let expr2_0 = MInst::VecDup { @@ -1511,7 +1511,7 @@ pub fn constructor_alu_rr_imm12( let pattern1_0 = arg1; let pattern2_0 = arg2; let pattern3_0 = arg3; - // Rule at src/isa/aarch64/inst.isle line 1418. + // Rule at src/isa/aarch64/inst.isle line 1410. let expr0_0: Type = I64; let expr1_0 = C::temp_writable_reg(ctx, expr0_0); let expr2_0 = constructor_operand_size(ctx, pattern1_0)?; @@ -1541,7 +1541,7 @@ pub fn constructor_alu_rrr_shift( let pattern2_0 = arg2; let pattern3_0 = arg3; let pattern4_0 = arg4; - // Rule at src/isa/aarch64/inst.isle line 1425. + // Rule at src/isa/aarch64/inst.isle line 1417. let expr0_0: Type = I64; let expr1_0 = C::temp_writable_reg(ctx, expr0_0); let expr2_0 = constructor_operand_size(ctx, pattern1_0)?; @@ -1572,7 +1572,7 @@ pub fn constructor_alu_rrr_extend( let pattern2_0 = arg2; let pattern3_0 = arg3; let pattern4_0 = arg4; - // Rule at src/isa/aarch64/inst.isle line 1432. + // Rule at src/isa/aarch64/inst.isle line 1424. let expr0_0: Type = I64; let expr1_0 = C::temp_writable_reg(ctx, expr0_0); let expr2_0 = constructor_operand_size(ctx, pattern1_0)?; @@ -1601,7 +1601,7 @@ pub fn constructor_alu_rr_extend_reg( let pattern1_0 = arg1; let pattern2_0 = arg2; let pattern3_0 = arg3; - // Rule at src/isa/aarch64/inst.isle line 1440. + // Rule at src/isa/aarch64/inst.isle line 1432. let expr0_0 = C::put_extended_in_reg(ctx, pattern3_0); let expr1_0 = C::get_extended_op(ctx, pattern3_0); let expr2_0 = @@ -1623,7 +1623,7 @@ pub fn constructor_alu_rrrr( let pattern2_0 = arg2; let pattern3_0 = arg3; let pattern4_0 = arg4; - // Rule at src/isa/aarch64/inst.isle line 1447. + // Rule at src/isa/aarch64/inst.isle line 1439. let expr0_0: Type = I64; let expr1_0 = C::temp_writable_reg(ctx, expr0_0); let expr2_0 = constructor_operand_size(ctx, pattern1_0)?; @@ -1650,7 +1650,7 @@ pub fn constructor_bit_rr( let pattern0_0 = arg0; let pattern1_0 = arg1; let pattern2_0 = arg2; - // Rule at src/isa/aarch64/inst.isle line 1454. + // Rule at src/isa/aarch64/inst.isle line 1446. let expr0_0: Type = I64; let expr1_0 = C::temp_writable_reg(ctx, expr0_0); let expr2_0 = constructor_operand_size(ctx, pattern1_0)?; @@ -1675,7 +1675,7 @@ pub fn constructor_add_with_flags_paired( let pattern0_0 = arg0; let pattern1_0 = arg1; let pattern2_0 = arg2; - // Rule at src/isa/aarch64/inst.isle line 1461. + // Rule at src/isa/aarch64/inst.isle line 1453. let expr0_0: Type = I64; let expr1_0 = C::temp_writable_reg(ctx, expr0_0); let expr2_0 = ALUOp::AddS; @@ -1705,7 +1705,7 @@ pub fn constructor_adc_paired( let pattern0_0 = arg0; let pattern1_0 = arg1; let pattern2_0 = arg2; - // Rule at src/isa/aarch64/inst.isle line 1469. + // Rule at src/isa/aarch64/inst.isle line 1461. let expr0_0: Type = I64; let expr1_0 = C::temp_writable_reg(ctx, expr0_0); let expr2_0 = ALUOp::Adc; @@ -1735,7 +1735,7 @@ pub fn constructor_sub_with_flags_paired( let pattern0_0 = arg0; let pattern1_0 = arg1; let pattern2_0 = arg2; - // Rule at src/isa/aarch64/inst.isle line 1477. + // Rule at src/isa/aarch64/inst.isle line 1469. let expr0_0: Type = I64; let expr1_0 = C::temp_writable_reg(ctx, expr0_0); let expr2_0 = ALUOp::SubS; @@ -1763,7 +1763,7 @@ pub fn constructor_cmp64_imm( ) -> Option { let pattern0_0 = arg0; let pattern1_0 = arg1; - // Rule at src/isa/aarch64/inst.isle line 1484. + // Rule at src/isa/aarch64/inst.isle line 1476. let expr0_0 = ALUOp::SubS; let expr1_0 = OperandSize::Size64; let expr2_0 = C::writable_zero_reg(ctx); @@ -1788,7 +1788,7 @@ pub fn constructor_sbc_paired( let pattern0_0 = arg0; let pattern1_0 = arg1; let pattern2_0 = arg2; - // Rule at src/isa/aarch64/inst.isle line 1491. + // Rule at src/isa/aarch64/inst.isle line 1483. let expr0_0: Type = I64; let expr1_0 = C::temp_writable_reg(ctx, expr0_0); let expr2_0 = ALUOp::Sbc; @@ -1818,7 +1818,7 @@ pub fn constructor_vec_misc( let pattern0_0 = arg0; let pattern1_0 = arg1; let pattern2_0 = arg2; - // Rule at src/isa/aarch64/inst.isle line 1499. + // Rule at src/isa/aarch64/inst.isle line 1491. let expr0_0: Type = I8X16; let expr1_0 = C::temp_writable_reg(ctx, expr0_0); let expr2_0 = MInst::VecMisc { @@ -1844,7 +1844,7 @@ pub fn constructor_vec_rrr_long( let pattern1_0 = arg1; let pattern2_0 = arg2; let pattern3_0 = arg3; - // Rule at src/isa/aarch64/inst.isle line 1506. + // Rule at src/isa/aarch64/inst.isle line 1498. let expr0_0: Type = I8X16; let expr1_0 = C::temp_writable_reg(ctx, expr0_0); let expr2_0 = MInst::VecRRRLong { @@ -1873,7 +1873,7 @@ pub fn constructor_vec_rrrr_long( let pattern2_0 = arg2; let pattern3_0 = arg3; let pattern4_0 = arg4; - // Rule at src/isa/aarch64/inst.isle line 1516. + // Rule at src/isa/aarch64/inst.isle line 1508. let expr0_0: Type = I8X16; let expr1_0 = C::temp_writable_reg(ctx, expr0_0); let expr2_0 = MInst::FpuMove128 { @@ -1903,7 +1903,7 @@ pub fn constructor_vec_rr_narrow( let pattern0_0 = arg0; let pattern1_0 = arg1; let pattern2_0 = arg2; - // Rule at src/isa/aarch64/inst.isle line 1524. + // Rule at src/isa/aarch64/inst.isle line 1516. let expr0_0: Type = I8X16; let expr1_0 = C::temp_writable_reg(ctx, expr0_0); let expr2_0 = MInst::VecRRNarrow { @@ -1927,7 +1927,7 @@ pub fn constructor_vec_rr_long( let pattern0_0 = arg0; let pattern1_0 = arg1; let pattern2_0 = arg2; - // Rule at src/isa/aarch64/inst.isle line 1531. + // Rule at src/isa/aarch64/inst.isle line 1523. let expr0_0: Type = I8X16; let expr1_0 = C::temp_writable_reg(ctx, expr0_0); let expr2_0 = MInst::VecRRLong { @@ -1949,7 +1949,7 @@ pub fn constructor_mov_to_fpu( ) -> Option { let pattern0_0 = arg0; let pattern1_0 = arg1; - // Rule at src/isa/aarch64/inst.isle line 1538. + // Rule at src/isa/aarch64/inst.isle line 1530. let expr0_0: Type = I8X16; let expr1_0 = C::temp_writable_reg(ctx, expr0_0); let expr2_0 = MInst::MovToFpu { @@ -1974,7 +1974,7 @@ pub fn constructor_mov_to_vec( let pattern1_0 = arg1; let pattern2_0 = arg2; let pattern3_0 = arg3; - // Rule at src/isa/aarch64/inst.isle line 1545. + // Rule at src/isa/aarch64/inst.isle line 1537. let expr0_0: Type = I8X16; let expr1_0 = C::temp_writable_reg(ctx, expr0_0); let expr2_0 = MInst::FpuMove128 { @@ -2003,7 +2003,7 @@ pub fn constructor_mov_from_vec( let pattern0_0 = arg0; let pattern1_0 = arg1; let pattern2_0 = arg2; - // Rule at src/isa/aarch64/inst.isle line 1553. + // Rule at src/isa/aarch64/inst.isle line 1545. let expr0_0: Type = I64; let expr1_0 = C::temp_writable_reg(ctx, expr0_0); let expr2_0 = MInst::MovFromVec { @@ -2029,7 +2029,7 @@ pub fn constructor_mov_from_vec_signed( let pattern1_0 = arg1; let pattern2_0 = arg2; let pattern3_0 = arg3; - // Rule at src/isa/aarch64/inst.isle line 1560. + // Rule at src/isa/aarch64/inst.isle line 1552. let expr0_0: Type = I64; let expr1_0 = C::temp_writable_reg(ctx, expr0_0); let expr2_0 = MInst::MovFromVecSigned { @@ -2056,7 +2056,7 @@ pub fn constructor_extend( let pattern1_0 = arg1; let pattern2_0 = arg2; let pattern3_0 = arg3; - // Rule at src/isa/aarch64/inst.isle line 1567. + // Rule at src/isa/aarch64/inst.isle line 1559. let expr0_0: Type = I64; let expr1_0 = C::temp_writable_reg(ctx, expr0_0); let expr2_0 = MInst::Extend { @@ -2075,7 +2075,7 @@ pub fn constructor_extend( pub fn constructor_load_acquire(ctx: &mut C, arg0: Type, arg1: Reg) -> Option { let pattern0_0 = arg0; let pattern1_0 = arg1; - // Rule at src/isa/aarch64/inst.isle line 1574. + // Rule at src/isa/aarch64/inst.isle line 1566. let expr0_0: Type = I64; let expr1_0 = C::temp_writable_reg(ctx, expr0_0); let expr2_0 = MInst::LoadAcquire { @@ -2098,7 +2098,7 @@ pub fn constructor_tst_imm( let pattern0_0 = arg0; let pattern1_0 = arg1; let pattern2_0 = arg2; - // Rule at src/isa/aarch64/inst.isle line 1584. + // Rule at src/isa/aarch64/inst.isle line 1576. let expr0_0 = ALUOp::AndS; let expr1_0 = constructor_operand_size(ctx, pattern0_0)?; let expr2_0 = C::writable_zero_reg(ctx); @@ -2123,7 +2123,7 @@ pub fn constructor_csel( let pattern0_0 = arg0; let pattern1_0 = arg1; let pattern2_0 = arg2; - // Rule at src/isa/aarch64/inst.isle line 1598. + // Rule at src/isa/aarch64/inst.isle line 1590. let expr0_0: Type = I64; let expr1_0 = C::temp_writable_reg(ctx, expr0_0); let expr2_0 = MInst::CSel { @@ -2145,7 +2145,7 @@ pub fn constructor_add(ctx: &mut C, arg0: Type, arg1: Reg, arg2: Reg let pattern0_0 = arg0; let pattern1_0 = arg1; let pattern2_0 = arg2; - // Rule at src/isa/aarch64/inst.isle line 1607. + // Rule at src/isa/aarch64/inst.isle line 1599. let expr0_0 = ALUOp::Add; let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?; return Some(expr1_0); @@ -2161,7 +2161,7 @@ pub fn constructor_add_imm( let pattern0_0 = arg0; let pattern1_0 = arg1; let pattern2_0 = arg2; - // Rule at src/isa/aarch64/inst.isle line 1610. + // Rule at src/isa/aarch64/inst.isle line 1602. let expr0_0 = ALUOp::Add; let expr1_0 = constructor_alu_rr_imm12(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?; return Some(expr1_0); @@ -2177,7 +2177,7 @@ pub fn constructor_add_extend( let pattern0_0 = arg0; let pattern1_0 = arg1; let pattern2_0 = arg2; - // Rule at src/isa/aarch64/inst.isle line 1613. + // Rule at src/isa/aarch64/inst.isle line 1605. let expr0_0 = ALUOp::Add; let expr1_0 = constructor_alu_rr_extend_reg(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?; return Some(expr1_0); @@ -2195,7 +2195,7 @@ pub fn constructor_add_shift( let pattern1_0 = arg1; let pattern2_0 = arg2; let pattern3_0 = arg3; - // Rule at src/isa/aarch64/inst.isle line 1616. + // Rule at src/isa/aarch64/inst.isle line 1608. let expr0_0 = ALUOp::Add; let expr1_0 = constructor_alu_rrr_shift( ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0, pattern3_0, @@ -2213,7 +2213,7 @@ pub fn constructor_add_vec( let pattern0_0 = arg0; let pattern1_0 = arg1; let pattern2_0 = arg2; - // Rule at src/isa/aarch64/inst.isle line 1619. + // Rule at src/isa/aarch64/inst.isle line 1611. let expr0_0 = VecALUOp::Add; let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?; return Some(expr1_0); @@ -2224,7 +2224,7 @@ pub fn constructor_sub(ctx: &mut C, arg0: Type, arg1: Reg, arg2: Reg let pattern0_0 = arg0; let pattern1_0 = arg1; let pattern2_0 = arg2; - // Rule at src/isa/aarch64/inst.isle line 1624. + // Rule at src/isa/aarch64/inst.isle line 1616. let expr0_0 = ALUOp::Sub; let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?; return Some(expr1_0); @@ -2240,7 +2240,7 @@ pub fn constructor_sub_imm( let pattern0_0 = arg0; let pattern1_0 = arg1; let pattern2_0 = arg2; - // Rule at src/isa/aarch64/inst.isle line 1627. + // Rule at src/isa/aarch64/inst.isle line 1619. let expr0_0 = ALUOp::Sub; let expr1_0 = constructor_alu_rr_imm12(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?; return Some(expr1_0); @@ -2256,7 +2256,7 @@ pub fn constructor_sub_extend( let pattern0_0 = arg0; let pattern1_0 = arg1; let pattern2_0 = arg2; - // Rule at src/isa/aarch64/inst.isle line 1630. + // Rule at src/isa/aarch64/inst.isle line 1622. let expr0_0 = ALUOp::Sub; let expr1_0 = constructor_alu_rr_extend_reg(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?; return Some(expr1_0); @@ -2274,7 +2274,7 @@ pub fn constructor_sub_shift( let pattern1_0 = arg1; let pattern2_0 = arg2; let pattern3_0 = arg3; - // Rule at src/isa/aarch64/inst.isle line 1633. + // Rule at src/isa/aarch64/inst.isle line 1625. let expr0_0 = ALUOp::Sub; let expr1_0 = constructor_alu_rrr_shift( ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0, pattern3_0, @@ -2292,7 +2292,7 @@ pub fn constructor_sub_vec( let pattern0_0 = arg0; let pattern1_0 = arg1; let pattern2_0 = arg2; - // Rule at src/isa/aarch64/inst.isle line 1636. + // Rule at src/isa/aarch64/inst.isle line 1628. let expr0_0 = VecALUOp::Sub; let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?; return Some(expr1_0); @@ -2310,7 +2310,7 @@ pub fn constructor_madd( let pattern1_0 = arg1; let pattern2_0 = arg2; let pattern3_0 = arg3; - // Rule at src/isa/aarch64/inst.isle line 1641. + // Rule at src/isa/aarch64/inst.isle line 1633. let expr0_0 = ALUOp3::MAdd; let expr1_0 = constructor_alu_rrrr( ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0, pattern3_0, @@ -2330,7 +2330,7 @@ pub fn constructor_msub( let pattern1_0 = arg1; let pattern2_0 = arg2; let pattern3_0 = arg3; - // Rule at src/isa/aarch64/inst.isle line 1646. + // Rule at src/isa/aarch64/inst.isle line 1638. let expr0_0 = ALUOp3::MSub; let expr1_0 = constructor_alu_rrrr( ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0, pattern3_0, @@ -2348,7 +2348,7 @@ pub fn constructor_uqadd( let pattern0_0 = arg0; let pattern1_0 = arg1; let pattern2_0 = arg2; - // Rule at src/isa/aarch64/inst.isle line 1650. + // Rule at src/isa/aarch64/inst.isle line 1642. let expr0_0 = VecALUOp::Uqadd; let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?; return Some(expr1_0); @@ -2364,7 +2364,7 @@ pub fn constructor_sqadd( let pattern0_0 = arg0; let pattern1_0 = arg1; let pattern2_0 = arg2; - // Rule at src/isa/aarch64/inst.isle line 1654. + // Rule at src/isa/aarch64/inst.isle line 1646. let expr0_0 = VecALUOp::Sqadd; let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?; return Some(expr1_0); @@ -2380,7 +2380,7 @@ pub fn constructor_uqsub( let pattern0_0 = arg0; let pattern1_0 = arg1; let pattern2_0 = arg2; - // Rule at src/isa/aarch64/inst.isle line 1658. + // Rule at src/isa/aarch64/inst.isle line 1650. let expr0_0 = VecALUOp::Uqsub; let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?; return Some(expr1_0); @@ -2396,7 +2396,7 @@ pub fn constructor_sqsub( let pattern0_0 = arg0; let pattern1_0 = arg1; let pattern2_0 = arg2; - // Rule at src/isa/aarch64/inst.isle line 1662. + // Rule at src/isa/aarch64/inst.isle line 1654. let expr0_0 = VecALUOp::Sqsub; let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?; return Some(expr1_0); @@ -2407,7 +2407,7 @@ pub fn constructor_umulh(ctx: &mut C, arg0: Type, arg1: Reg, arg2: R let pattern0_0 = arg0; let pattern1_0 = arg1; let pattern2_0 = arg2; - // Rule at src/isa/aarch64/inst.isle line 1666. + // Rule at src/isa/aarch64/inst.isle line 1658. let expr0_0 = ALUOp::UMulH; let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?; return Some(expr1_0); @@ -2418,7 +2418,7 @@ pub fn constructor_smulh(ctx: &mut C, arg0: Type, arg1: Reg, arg2: R let pattern0_0 = arg0; let pattern1_0 = arg1; let pattern2_0 = arg2; - // Rule at src/isa/aarch64/inst.isle line 1670. + // Rule at src/isa/aarch64/inst.isle line 1662. let expr0_0 = ALUOp::SMulH; let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?; return Some(expr1_0); @@ -2434,7 +2434,7 @@ pub fn constructor_mul( let pattern0_0 = arg0; let pattern1_0 = arg1; let pattern2_0 = arg2; - // Rule at src/isa/aarch64/inst.isle line 1674. + // Rule at src/isa/aarch64/inst.isle line 1666. let expr0_0 = VecALUOp::Mul; let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?; return Some(expr1_0); @@ -2444,7 +2444,7 @@ pub fn constructor_mul( pub fn constructor_neg(ctx: &mut C, arg0: Reg, arg1: &VectorSize) -> Option { let pattern0_0 = arg0; let pattern1_0 = arg1; - // Rule at src/isa/aarch64/inst.isle line 1678. + // Rule at src/isa/aarch64/inst.isle line 1670. let expr0_0 = VecMisc2::Neg; let expr1_0 = constructor_vec_misc(ctx, &expr0_0, pattern0_0, pattern1_0)?; return Some(expr1_0); @@ -2454,7 +2454,7 @@ pub fn constructor_neg(ctx: &mut C, arg0: Reg, arg1: &VectorSize) -> pub fn constructor_rev64(ctx: &mut C, arg0: Reg, arg1: &VectorSize) -> Option { let pattern0_0 = arg0; let pattern1_0 = arg1; - // Rule at src/isa/aarch64/inst.isle line 1682. + // Rule at src/isa/aarch64/inst.isle line 1674. let expr0_0 = VecMisc2::Rev64; let expr1_0 = constructor_vec_misc(ctx, &expr0_0, pattern0_0, pattern1_0)?; return Some(expr1_0); @@ -2464,7 +2464,7 @@ pub fn constructor_rev64(ctx: &mut C, arg0: Reg, arg1: &VectorSize) pub fn constructor_xtn64(ctx: &mut C, arg0: Reg, arg1: bool) -> Option { let pattern0_0 = arg0; let pattern1_0 = arg1; - // Rule at src/isa/aarch64/inst.isle line 1686. + // Rule at src/isa/aarch64/inst.isle line 1678. let expr0_0 = VecRRNarrowOp::Xtn64; let expr1_0 = constructor_vec_rr_narrow(ctx, &expr0_0, pattern0_0, pattern1_0)?; return Some(expr1_0); @@ -2480,7 +2480,7 @@ pub fn constructor_addp( let pattern0_0 = arg0; let pattern1_0 = arg1; let pattern2_0 = arg2; - // Rule at src/isa/aarch64/inst.isle line 1690. + // Rule at src/isa/aarch64/inst.isle line 1682. let expr0_0 = VecALUOp::Addp; let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?; return Some(expr1_0); @@ -2490,7 +2490,7 @@ pub fn constructor_addp( pub fn constructor_addv(ctx: &mut C, arg0: Reg, arg1: &VectorSize) -> Option { let pattern0_0 = arg0; let pattern1_0 = arg1; - // Rule at src/isa/aarch64/inst.isle line 1694. + // Rule at src/isa/aarch64/inst.isle line 1686. let expr0_0 = VecLanesOp::Addv; let expr1_0 = constructor_vec_lanes(ctx, &expr0_0, pattern0_0, pattern1_0)?; return Some(expr1_0); @@ -2500,7 +2500,7 @@ pub fn constructor_addv(ctx: &mut C, arg0: Reg, arg1: &VectorSize) - pub fn constructor_shll32(ctx: &mut C, arg0: Reg, arg1: bool) -> Option { let pattern0_0 = arg0; let pattern1_0 = arg1; - // Rule at src/isa/aarch64/inst.isle line 1698. + // Rule at src/isa/aarch64/inst.isle line 1690. let expr0_0 = VecRRLongOp::Shll32; let expr1_0 = constructor_vec_rr_long(ctx, &expr0_0, pattern0_0, pattern1_0)?; return Some(expr1_0); @@ -2518,7 +2518,7 @@ pub fn constructor_umlal32( let pattern1_0 = arg1; let pattern2_0 = arg2; let pattern3_0 = arg3; - // Rule at src/isa/aarch64/inst.isle line 1702. + // Rule at src/isa/aarch64/inst.isle line 1694. let expr0_0 = VecRRRLongOp::Umlal32; let expr1_0 = constructor_vec_rrrr_long( ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0, pattern3_0, @@ -2536,7 +2536,7 @@ pub fn constructor_smull8( let pattern0_0 = arg0; let pattern1_0 = arg1; let pattern2_0 = arg2; - // Rule at src/isa/aarch64/inst.isle line 1706. + // Rule at src/isa/aarch64/inst.isle line 1698. let expr0_0 = VecRRRLongOp::Smull8; let expr1_0 = constructor_vec_rrr_long(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?; return Some(expr1_0); @@ -2552,7 +2552,7 @@ pub fn constructor_umull8( let pattern0_0 = arg0; let pattern1_0 = arg1; let pattern2_0 = arg2; - // Rule at src/isa/aarch64/inst.isle line 1710. + // Rule at src/isa/aarch64/inst.isle line 1702. let expr0_0 = VecRRRLongOp::Umull8; let expr1_0 = constructor_vec_rrr_long(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?; return Some(expr1_0); @@ -2568,7 +2568,7 @@ pub fn constructor_smull16( let pattern0_0 = arg0; let pattern1_0 = arg1; let pattern2_0 = arg2; - // Rule at src/isa/aarch64/inst.isle line 1714. + // Rule at src/isa/aarch64/inst.isle line 1706. let expr0_0 = VecRRRLongOp::Smull16; let expr1_0 = constructor_vec_rrr_long(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?; return Some(expr1_0); @@ -2584,7 +2584,7 @@ pub fn constructor_umull16( let pattern0_0 = arg0; let pattern1_0 = arg1; let pattern2_0 = arg2; - // Rule at src/isa/aarch64/inst.isle line 1718. + // Rule at src/isa/aarch64/inst.isle line 1710. let expr0_0 = VecRRRLongOp::Umull16; let expr1_0 = constructor_vec_rrr_long(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?; return Some(expr1_0); @@ -2600,7 +2600,7 @@ pub fn constructor_smull32( let pattern0_0 = arg0; let pattern1_0 = arg1; let pattern2_0 = arg2; - // Rule at src/isa/aarch64/inst.isle line 1722. + // Rule at src/isa/aarch64/inst.isle line 1714. let expr0_0 = VecRRRLongOp::Smull32; let expr1_0 = constructor_vec_rrr_long(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?; return Some(expr1_0); @@ -2616,7 +2616,7 @@ pub fn constructor_umull32( let pattern0_0 = arg0; let pattern1_0 = arg1; let pattern2_0 = arg2; - // Rule at src/isa/aarch64/inst.isle line 1726. + // Rule at src/isa/aarch64/inst.isle line 1718. let expr0_0 = VecRRRLongOp::Umull32; let expr1_0 = constructor_vec_rrr_long(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?; return Some(expr1_0); @@ -2627,7 +2627,7 @@ pub fn constructor_asr(ctx: &mut C, arg0: Type, arg1: Reg, arg2: Reg let pattern0_0 = arg0; let pattern1_0 = arg1; let pattern2_0 = arg2; - // Rule at src/isa/aarch64/inst.isle line 1730. + // Rule at src/isa/aarch64/inst.isle line 1722. let expr0_0 = ALUOp::Asr; let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?; return Some(expr1_0); @@ -2643,7 +2643,7 @@ pub fn constructor_asr_imm( let pattern0_0 = arg0; let pattern1_0 = arg1; let pattern2_0 = arg2; - // Rule at src/isa/aarch64/inst.isle line 1733. + // Rule at src/isa/aarch64/inst.isle line 1725. let expr0_0 = ALUOp::Asr; let expr1_0 = constructor_alu_rr_imm_shift(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?; return Some(expr1_0); @@ -2654,7 +2654,7 @@ pub fn constructor_lsr(ctx: &mut C, arg0: Type, arg1: Reg, arg2: Reg let pattern0_0 = arg0; let pattern1_0 = arg1; let pattern2_0 = arg2; - // Rule at src/isa/aarch64/inst.isle line 1737. + // Rule at src/isa/aarch64/inst.isle line 1729. let expr0_0 = ALUOp::Lsr; let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?; return Some(expr1_0); @@ -2670,7 +2670,7 @@ pub fn constructor_lsr_imm( let pattern0_0 = arg0; let pattern1_0 = arg1; let pattern2_0 = arg2; - // Rule at src/isa/aarch64/inst.isle line 1740. + // Rule at src/isa/aarch64/inst.isle line 1732. let expr0_0 = ALUOp::Lsr; let expr1_0 = constructor_alu_rr_imm_shift(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?; return Some(expr1_0); @@ -2681,7 +2681,7 @@ pub fn constructor_lsl(ctx: &mut C, arg0: Type, arg1: Reg, arg2: Reg let pattern0_0 = arg0; let pattern1_0 = arg1; let pattern2_0 = arg2; - // Rule at src/isa/aarch64/inst.isle line 1744. + // Rule at src/isa/aarch64/inst.isle line 1736. let expr0_0 = ALUOp::Lsl; let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?; return Some(expr1_0); @@ -2697,7 +2697,7 @@ pub fn constructor_lsl_imm( let pattern0_0 = arg0; let pattern1_0 = arg1; let pattern2_0 = arg2; - // Rule at src/isa/aarch64/inst.isle line 1747. + // Rule at src/isa/aarch64/inst.isle line 1739. let expr0_0 = ALUOp::Lsl; let expr1_0 = constructor_alu_rr_imm_shift(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?; return Some(expr1_0); @@ -2713,7 +2713,7 @@ pub fn constructor_a64_udiv( let pattern0_0 = arg0; let pattern1_0 = arg1; let pattern2_0 = arg2; - // Rule at src/isa/aarch64/inst.isle line 1751. + // Rule at src/isa/aarch64/inst.isle line 1743. let expr0_0 = ALUOp::UDiv; let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?; return Some(expr1_0); @@ -2729,7 +2729,7 @@ pub fn constructor_a64_sdiv( let pattern0_0 = arg0; let pattern1_0 = arg1; let pattern2_0 = arg2; - // Rule at src/isa/aarch64/inst.isle line 1755. + // Rule at src/isa/aarch64/inst.isle line 1747. let expr0_0 = ALUOp::SDiv; let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?; return Some(expr1_0); @@ -2739,7 +2739,7 @@ pub fn constructor_a64_sdiv( pub fn constructor_not(ctx: &mut C, arg0: Reg, arg1: &VectorSize) -> Option { let pattern0_0 = arg0; let pattern1_0 = arg1; - // Rule at src/isa/aarch64/inst.isle line 1759. + // Rule at src/isa/aarch64/inst.isle line 1751. let expr0_0 = VecMisc2::Not; let expr1_0 = constructor_vec_misc(ctx, &expr0_0, pattern0_0, pattern1_0)?; return Some(expr1_0); @@ -2755,7 +2755,7 @@ pub fn constructor_orr_not( let pattern0_0 = arg0; let pattern1_0 = arg1; let pattern2_0 = arg2; - // Rule at src/isa/aarch64/inst.isle line 1764. + // Rule at src/isa/aarch64/inst.isle line 1756. let expr0_0 = ALUOp::OrrNot; let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?; return Some(expr1_0); @@ -2773,7 +2773,7 @@ pub fn constructor_orr_not_shift( let pattern1_0 = arg1; let pattern2_0 = arg2; let pattern3_0 = arg3; - // Rule at src/isa/aarch64/inst.isle line 1767. + // Rule at src/isa/aarch64/inst.isle line 1759. let expr0_0 = ALUOp::OrrNot; let expr1_0 = constructor_alu_rrr_shift( ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0, pattern3_0, @@ -2786,7 +2786,7 @@ pub fn constructor_orr(ctx: &mut C, arg0: Type, arg1: Reg, arg2: Reg let pattern0_0 = arg0; let pattern1_0 = arg1; let pattern2_0 = arg2; - // Rule at src/isa/aarch64/inst.isle line 1772. + // Rule at src/isa/aarch64/inst.isle line 1764. let expr0_0 = ALUOp::Orr; let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?; return Some(expr1_0); @@ -2802,7 +2802,7 @@ pub fn constructor_orr_imm( let pattern0_0 = arg0; let pattern1_0 = arg1; let pattern2_0 = arg2; - // Rule at src/isa/aarch64/inst.isle line 1775. + // Rule at src/isa/aarch64/inst.isle line 1767. let expr0_0 = ALUOp::Orr; let expr1_0 = constructor_alu_rr_imm_logic(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?; return Some(expr1_0); @@ -2818,7 +2818,7 @@ pub fn constructor_orr_vec( let pattern0_0 = arg0; let pattern1_0 = arg1; let pattern2_0 = arg2; - // Rule at src/isa/aarch64/inst.isle line 1778. + // Rule at src/isa/aarch64/inst.isle line 1770. let expr0_0 = VecALUOp::Orr; let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?; return Some(expr1_0); @@ -2834,7 +2834,7 @@ pub fn constructor_and_imm( let pattern0_0 = arg0; let pattern1_0 = arg1; let pattern2_0 = arg2; - // Rule at src/isa/aarch64/inst.isle line 1783. + // Rule at src/isa/aarch64/inst.isle line 1775. let expr0_0 = ALUOp::And; let expr1_0 = constructor_alu_rr_imm_logic(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?; return Some(expr1_0); @@ -2850,7 +2850,7 @@ pub fn constructor_and_vec( let pattern0_0 = arg0; let pattern1_0 = arg1; let pattern2_0 = arg2; - // Rule at src/isa/aarch64/inst.isle line 1786. + // Rule at src/isa/aarch64/inst.isle line 1778. let expr0_0 = VecALUOp::And; let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?; return Some(expr1_0); @@ -2866,7 +2866,7 @@ pub fn constructor_eor_vec( let pattern0_0 = arg0; let pattern1_0 = arg1; let pattern2_0 = arg2; - // Rule at src/isa/aarch64/inst.isle line 1790. + // Rule at src/isa/aarch64/inst.isle line 1782. let expr0_0 = VecALUOp::Eor; let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?; return Some(expr1_0); @@ -2882,7 +2882,7 @@ pub fn constructor_bic_vec( let pattern0_0 = arg0; let pattern1_0 = arg1; let pattern2_0 = arg2; - // Rule at src/isa/aarch64/inst.isle line 1794. + // Rule at src/isa/aarch64/inst.isle line 1786. let expr0_0 = VecALUOp::Bic; let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?; return Some(expr1_0); @@ -2898,7 +2898,7 @@ pub fn constructor_sshl( let pattern0_0 = arg0; let pattern1_0 = arg1; let pattern2_0 = arg2; - // Rule at src/isa/aarch64/inst.isle line 1798. + // Rule at src/isa/aarch64/inst.isle line 1790. let expr0_0 = VecALUOp::Sshl; let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?; return Some(expr1_0); @@ -2914,7 +2914,7 @@ pub fn constructor_ushl( let pattern0_0 = arg0; let pattern1_0 = arg1; let pattern2_0 = arg2; - // Rule at src/isa/aarch64/inst.isle line 1802. + // Rule at src/isa/aarch64/inst.isle line 1794. let expr0_0 = VecALUOp::Ushl; let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?; return Some(expr1_0); @@ -2930,7 +2930,7 @@ pub fn constructor_a64_rotr( let pattern0_0 = arg0; let pattern1_0 = arg1; let pattern2_0 = arg2; - // Rule at src/isa/aarch64/inst.isle line 1807. + // Rule at src/isa/aarch64/inst.isle line 1799. let expr0_0 = ALUOp::RotR; let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?; return Some(expr1_0); @@ -2946,7 +2946,7 @@ pub fn constructor_a64_rotr_imm( let pattern0_0 = arg0; let pattern1_0 = arg1; let pattern2_0 = arg2; - // Rule at src/isa/aarch64/inst.isle line 1810. + // Rule at src/isa/aarch64/inst.isle line 1802. let expr0_0 = ALUOp::RotR; let expr1_0 = constructor_alu_rr_imm_shift(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?; return Some(expr1_0); @@ -2956,7 +2956,7 @@ pub fn constructor_a64_rotr_imm( pub fn constructor_rbit(ctx: &mut C, arg0: Type, arg1: Reg) -> Option { let pattern0_0 = arg0; let pattern1_0 = arg1; - // Rule at src/isa/aarch64/inst.isle line 1815. + // Rule at src/isa/aarch64/inst.isle line 1807. let expr0_0 = BitOp::RBit; let expr1_0 = constructor_bit_rr(ctx, &expr0_0, pattern0_0, pattern1_0)?; return Some(expr1_0); @@ -2966,7 +2966,7 @@ pub fn constructor_rbit(ctx: &mut C, arg0: Type, arg1: Reg) -> Optio pub fn constructor_a64_clz(ctx: &mut C, arg0: Type, arg1: Reg) -> Option { let pattern0_0 = arg0; let pattern1_0 = arg1; - // Rule at src/isa/aarch64/inst.isle line 1820. + // Rule at src/isa/aarch64/inst.isle line 1812. let expr0_0 = BitOp::Clz; let expr1_0 = constructor_bit_rr(ctx, &expr0_0, pattern0_0, pattern1_0)?; return Some(expr1_0); @@ -2976,7 +2976,7 @@ pub fn constructor_a64_clz(ctx: &mut C, arg0: Type, arg1: Reg) -> Op pub fn constructor_a64_cls(ctx: &mut C, arg0: Type, arg1: Reg) -> Option { let pattern0_0 = arg0; let pattern1_0 = arg1; - // Rule at src/isa/aarch64/inst.isle line 1825. + // Rule at src/isa/aarch64/inst.isle line 1817. let expr0_0 = BitOp::Cls; let expr1_0 = constructor_bit_rr(ctx, &expr0_0, pattern0_0, pattern1_0)?; return Some(expr1_0); @@ -2987,7 +2987,7 @@ pub fn constructor_eon(ctx: &mut C, arg0: Type, arg1: Reg, arg2: Reg let pattern0_0 = arg0; let pattern1_0 = arg1; let pattern2_0 = arg2; - // Rule at src/isa/aarch64/inst.isle line 1830. + // Rule at src/isa/aarch64/inst.isle line 1822. let expr0_0 = ALUOp::EorNot; let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?; return Some(expr1_0); @@ -2997,7 +2997,7 @@ pub fn constructor_eon(ctx: &mut C, arg0: Type, arg1: Reg, arg2: Reg pub fn constructor_vec_cnt(ctx: &mut C, arg0: Reg, arg1: &VectorSize) -> Option { let pattern0_0 = arg0; let pattern1_0 = arg1; - // Rule at src/isa/aarch64/inst.isle line 1835. + // Rule at src/isa/aarch64/inst.isle line 1827. let expr0_0 = VecMisc2::Cnt; let expr1_0 = constructor_vec_misc(ctx, &expr0_0, pattern0_0, pattern1_0)?; return Some(expr1_0); @@ -3014,7 +3014,7 @@ pub fn constructor_imm(ctx: &mut C, arg0: Type, arg1: u64) -> Option }; if let Some(pattern3_0) = closure3() { if let Some(pattern4_0) = C::imm_logic_from_u64(ctx, pattern2_0, pattern3_0) { - // Rule at src/isa/aarch64/inst.isle line 1850. + // Rule at src/isa/aarch64/inst.isle line 1842. let expr0_0: Type = I64; let expr1_0 = C::zero_reg(ctx); let expr2_0 = constructor_orr_imm(ctx, expr0_0, expr1_0, pattern4_0)?; @@ -3022,18 +3022,18 @@ pub fn constructor_imm(ctx: &mut C, arg0: Type, arg1: u64) -> Option } } if let Some(pattern3_0) = C::move_wide_const_from_u64(ctx, pattern2_0) { - // Rule at src/isa/aarch64/inst.isle line 1842. + // Rule at src/isa/aarch64/inst.isle line 1834. let expr0_0 = OperandSize::Size64; let expr1_0 = constructor_movz(ctx, pattern3_0, &expr0_0)?; return Some(expr1_0); } if let Some(pattern3_0) = C::move_wide_const_from_negated_u64(ctx, pattern2_0) { - // Rule at src/isa/aarch64/inst.isle line 1846. + // Rule at src/isa/aarch64/inst.isle line 1838. let expr0_0 = OperandSize::Size64; let expr1_0 = constructor_movn(ctx, pattern3_0, &expr0_0)?; return Some(expr1_0); } - // Rule at src/isa/aarch64/inst.isle line 1857. + // Rule at src/isa/aarch64/inst.isle line 1849. let expr0_0 = C::load_constant64_full(ctx, pattern2_0); return Some(expr0_0); } @@ -3045,17 +3045,17 @@ pub fn constructor_put_in_reg_sext32(ctx: &mut C, arg0: Value) -> Op let pattern0_0 = arg0; let pattern1_0 = C::value_type(ctx, pattern0_0); if pattern1_0 == I32 { - // Rule at src/isa/aarch64/inst.isle line 1868. + // Rule at src/isa/aarch64/inst.isle line 1860. let expr0_0 = C::put_in_reg(ctx, pattern0_0); return Some(expr0_0); } if pattern1_0 == I64 { - // Rule at src/isa/aarch64/inst.isle line 1869. + // Rule at src/isa/aarch64/inst.isle line 1861. let expr0_0 = C::put_in_reg(ctx, pattern0_0); return Some(expr0_0); } if let Some(pattern2_0) = C::fits_in_32(ctx, pattern1_0) { - // Rule at src/isa/aarch64/inst.isle line 1864. + // Rule at src/isa/aarch64/inst.isle line 1856. let expr0_0 = C::put_in_reg(ctx, pattern0_0); let expr1_0: bool = true; let expr2_0 = C::ty_bits(ctx, pattern2_0); @@ -3071,17 +3071,17 @@ pub fn constructor_put_in_reg_zext32(ctx: &mut C, arg0: Value) -> Op let pattern0_0 = arg0; let pattern1_0 = C::value_type(ctx, pattern0_0); if pattern1_0 == I32 { - // Rule at src/isa/aarch64/inst.isle line 1877. + // Rule at src/isa/aarch64/inst.isle line 1869. let expr0_0 = C::put_in_reg(ctx, pattern0_0); return Some(expr0_0); } if pattern1_0 == I64 { - // Rule at src/isa/aarch64/inst.isle line 1878. + // Rule at src/isa/aarch64/inst.isle line 1870. let expr0_0 = C::put_in_reg(ctx, pattern0_0); return Some(expr0_0); } if let Some(pattern2_0) = C::fits_in_32(ctx, pattern1_0) { - // Rule at src/isa/aarch64/inst.isle line 1873. + // Rule at src/isa/aarch64/inst.isle line 1865. let expr0_0 = C::put_in_reg(ctx, pattern0_0); let expr1_0: bool = false; let expr2_0 = C::ty_bits(ctx, pattern2_0); @@ -3097,12 +3097,12 @@ pub fn constructor_put_in_reg_sext64(ctx: &mut C, arg0: Value) -> Op let pattern0_0 = arg0; let pattern1_0 = C::value_type(ctx, pattern0_0); if pattern1_0 == I64 { - // Rule at src/isa/aarch64/inst.isle line 1886. + // Rule at src/isa/aarch64/inst.isle line 1878. let expr0_0 = C::put_in_reg(ctx, pattern0_0); return Some(expr0_0); } if let Some(pattern2_0) = C::fits_in_32(ctx, pattern1_0) { - // Rule at src/isa/aarch64/inst.isle line 1882. + // Rule at src/isa/aarch64/inst.isle line 1874. let expr0_0 = C::put_in_reg(ctx, pattern0_0); let expr1_0: bool = true; let expr2_0 = C::ty_bits(ctx, pattern2_0); @@ -3118,12 +3118,12 @@ pub fn constructor_put_in_reg_zext64(ctx: &mut C, arg0: Value) -> Op let pattern0_0 = arg0; let pattern1_0 = C::value_type(ctx, pattern0_0); if pattern1_0 == I64 { - // Rule at src/isa/aarch64/inst.isle line 1894. + // Rule at src/isa/aarch64/inst.isle line 1886. let expr0_0 = C::put_in_reg(ctx, pattern0_0); return Some(expr0_0); } if let Some(pattern2_0) = C::fits_in_32(ctx, pattern1_0) { - // Rule at src/isa/aarch64/inst.isle line 1890. + // Rule at src/isa/aarch64/inst.isle line 1882. let expr0_0 = C::put_in_reg(ctx, pattern0_0); let expr1_0: bool = false; let expr2_0 = C::ty_bits(ctx, pattern2_0); @@ -3137,7 +3137,7 @@ pub fn constructor_put_in_reg_zext64(ctx: &mut C, arg0: Value) -> Op // Generated as internal constructor for term trap_if_zero_divisor. pub fn constructor_trap_if_zero_divisor(ctx: &mut C, arg0: Reg) -> Option { let pattern0_0 = arg0; - // Rule at src/isa/aarch64/inst.isle line 1899. + // Rule at src/isa/aarch64/inst.isle line 1891. let expr0_0 = C::cond_br_zero(ctx, pattern0_0); let expr1_0 = C::trap_code_division_by_zero(ctx); let expr2_0 = MInst::TrapIf { @@ -3152,12 +3152,12 @@ pub fn constructor_trap_if_zero_divisor(ctx: &mut C, arg0: Reg) -> O pub fn constructor_size_from_ty(ctx: &mut C, arg0: Type) -> Option { let pattern0_0 = arg0; if pattern0_0 == I64 { - // Rule at src/isa/aarch64/inst.isle line 1905. + // Rule at src/isa/aarch64/inst.isle line 1897. let expr0_0 = OperandSize::Size64; return Some(expr0_0); } if let Some(pattern1_0) = C::fits_in_32(ctx, pattern0_0) { - // Rule at src/isa/aarch64/inst.isle line 1904. + // Rule at src/isa/aarch64/inst.isle line 1896. let expr0_0 = OperandSize::Size32; return Some(expr0_0); } @@ -3174,7 +3174,7 @@ pub fn constructor_trap_if_div_overflow( let pattern0_0 = arg0; let pattern1_0 = arg1; let pattern2_0 = arg2; - // Rule at src/isa/aarch64/inst.isle line 1911. + // Rule at src/isa/aarch64/inst.isle line 1903. let expr0_0 = ALUOp::AddS; let expr1_0 = constructor_operand_size(ctx, pattern0_0)?; let expr2_0 = C::writable_zero_reg(ctx); @@ -3243,7 +3243,7 @@ pub fn constructor_alu_rs_imm_logic_commutative( C::imm_logic_from_imm64(ctx, pattern5_1, pattern7_0) { let pattern9_0 = arg3; - // Rule at src/isa/aarch64/inst.isle line 1956. + // Rule at src/isa/aarch64/inst.isle line 1948. let expr0_0 = C::put_in_reg(ctx, pattern9_0); let expr1_0 = constructor_alu_rr_imm_logic( ctx, pattern0_0, pattern1_0, expr0_0, pattern8_0, @@ -3275,7 +3275,7 @@ pub fn constructor_alu_rs_imm_logic_commutative( C::lshl_from_imm64(ctx, pattern10_1, pattern12_0) { let pattern14_0 = arg3; - // Rule at src/isa/aarch64/inst.isle line 1962. + // Rule at src/isa/aarch64/inst.isle line 1954. let expr0_0 = C::put_in_reg(ctx, pattern14_0); let expr1_0 = C::put_in_reg(ctx, pattern7_0); let expr2_0 = constructor_alu_rrr_shift( @@ -3313,7 +3313,7 @@ pub fn constructor_alu_rs_imm_logic_commutative( if let Some(pattern9_0) = C::imm_logic_from_imm64(ctx, pattern6_1, pattern8_0) { - // Rule at src/isa/aarch64/inst.isle line 1954. + // Rule at src/isa/aarch64/inst.isle line 1946. let expr0_0 = C::put_in_reg(ctx, pattern2_0); let expr1_0 = constructor_alu_rr_imm_logic( ctx, pattern0_0, pattern1_0, expr0_0, pattern9_0, @@ -3344,7 +3344,7 @@ pub fn constructor_alu_rs_imm_logic_commutative( if let Some(pattern14_0) = C::lshl_from_imm64(ctx, pattern11_1, pattern13_0) { - // Rule at src/isa/aarch64/inst.isle line 1960. + // Rule at src/isa/aarch64/inst.isle line 1952. let expr0_0 = C::put_in_reg(ctx, pattern2_0); let expr1_0 = C::put_in_reg(ctx, pattern8_0); let expr2_0 = constructor_alu_rrr_shift( @@ -3366,7 +3366,7 @@ pub fn constructor_alu_rs_imm_logic_commutative( _ => {} } } - // Rule at src/isa/aarch64/inst.isle line 1950. + // Rule at src/isa/aarch64/inst.isle line 1942. let expr0_0 = C::put_in_reg(ctx, pattern2_0); let expr1_0 = C::put_in_reg(ctx, pattern3_0); let expr2_0 = constructor_alu_rrr(ctx, pattern0_0, pattern1_0, expr0_0, expr1_0)?; @@ -3400,7 +3400,7 @@ pub fn constructor_alu_rs_imm_logic( if let Some(pattern9_0) = C::imm_logic_from_imm64(ctx, pattern6_1, pattern8_0) { - // Rule at src/isa/aarch64/inst.isle line 1970. + // Rule at src/isa/aarch64/inst.isle line 1962. let expr0_0 = C::put_in_reg(ctx, pattern2_0); let expr1_0 = constructor_alu_rr_imm_logic( ctx, pattern0_0, pattern1_0, expr0_0, pattern9_0, @@ -3431,7 +3431,7 @@ pub fn constructor_alu_rs_imm_logic( if let Some(pattern14_0) = C::lshl_from_imm64(ctx, pattern11_1, pattern13_0) { - // Rule at src/isa/aarch64/inst.isle line 1972. + // Rule at src/isa/aarch64/inst.isle line 1964. let expr0_0 = C::put_in_reg(ctx, pattern2_0); let expr1_0 = C::put_in_reg(ctx, pattern8_0); let expr2_0 = constructor_alu_rrr_shift( @@ -3453,7 +3453,7 @@ pub fn constructor_alu_rs_imm_logic( _ => {} } } - // Rule at src/isa/aarch64/inst.isle line 1968. + // Rule at src/isa/aarch64/inst.isle line 1960. let expr0_0 = C::put_in_reg(ctx, pattern2_0); let expr1_0 = C::put_in_reg(ctx, pattern3_0); let expr2_0 = constructor_alu_rrr(ctx, pattern0_0, pattern1_0, expr0_0, expr1_0)?; @@ -3472,7 +3472,7 @@ pub fn constructor_i128_alu_bitop( let pattern1_0 = arg1; let pattern2_0 = arg2; let pattern3_0 = arg3; - // Rule at src/isa/aarch64/inst.isle line 1980. + // Rule at src/isa/aarch64/inst.isle line 1972. let expr0_0 = C::put_in_regs(ctx, pattern2_0); let expr1_0: usize = 0; let expr2_0 = C::value_regs_get(ctx, expr0_0, expr1_0); @@ -3499,7 +3499,7 @@ pub fn constructor_float_cmp_zero( let pattern0_0 = arg0; let pattern1_0 = arg1; let pattern2_0 = arg2; - // Rule at src/isa/aarch64/inst.isle line 2020. + // Rule at src/isa/aarch64/inst.isle line 2012. let expr0_0 = C::float_cc_cmp_zero_to_vec_misc_op(ctx, pattern0_0); let expr1_0 = constructor_vec_misc(ctx, &expr0_0, pattern1_0, pattern2_0)?; return Some(expr1_0); @@ -3515,7 +3515,7 @@ pub fn constructor_float_cmp_zero_swap( let pattern0_0 = arg0; let pattern1_0 = arg1; let pattern2_0 = arg2; - // Rule at src/isa/aarch64/inst.isle line 2025. + // Rule at src/isa/aarch64/inst.isle line 2017. let expr0_0 = C::float_cc_cmp_zero_to_vec_misc_op_swap(ctx, pattern0_0); let expr1_0 = constructor_vec_misc(ctx, &expr0_0, pattern1_0, pattern2_0)?; return Some(expr1_0); @@ -3525,7 +3525,7 @@ pub fn constructor_float_cmp_zero_swap( pub fn constructor_fcmeq0(ctx: &mut C, arg0: Reg, arg1: &VectorSize) -> Option { let pattern0_0 = arg0; let pattern1_0 = arg1; - // Rule at src/isa/aarch64/inst.isle line 2030. + // Rule at src/isa/aarch64/inst.isle line 2022. let expr0_0 = VecMisc2::Fcmeq0; let expr1_0 = constructor_vec_misc(ctx, &expr0_0, pattern0_0, pattern1_0)?; return Some(expr1_0); @@ -3541,7 +3541,7 @@ pub fn constructor_int_cmp_zero( let pattern0_0 = arg0; let pattern1_0 = arg1; let pattern2_0 = arg2; - // Rule at src/isa/aarch64/inst.isle line 2056. + // Rule at src/isa/aarch64/inst.isle line 2048. let expr0_0 = C::int_cc_cmp_zero_to_vec_misc_op(ctx, pattern0_0); let expr1_0 = constructor_vec_misc(ctx, &expr0_0, pattern1_0, pattern2_0)?; return Some(expr1_0); @@ -3557,7 +3557,7 @@ pub fn constructor_int_cmp_zero_swap( let pattern0_0 = arg0; let pattern1_0 = arg1; let pattern2_0 = arg2; - // Rule at src/isa/aarch64/inst.isle line 2061. + // Rule at src/isa/aarch64/inst.isle line 2053. let expr0_0 = C::int_cc_cmp_zero_to_vec_misc_op_swap(ctx, pattern0_0); let expr1_0 = constructor_vec_misc(ctx, &expr0_0, pattern1_0, pattern2_0)?; return Some(expr1_0); @@ -3567,7 +3567,7 @@ pub fn constructor_int_cmp_zero_swap( pub fn constructor_cmeq0(ctx: &mut C, arg0: Reg, arg1: &VectorSize) -> Option { let pattern0_0 = arg0; let pattern1_0 = arg1; - // Rule at src/isa/aarch64/inst.isle line 2066. + // Rule at src/isa/aarch64/inst.isle line 2058. let expr0_0 = VecMisc2::Cmeq0; let expr1_0 = constructor_vec_misc(ctx, &expr0_0, pattern0_0, pattern1_0)?; return Some(expr1_0);