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Remove sig data arg and ret fields to reduce size (#5319)

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* Remove sig data arg and ret fields to reduce size

* Update cranelift/codegen/src/machinst/abi.rs

Co-authored-by: Jamey Sharp <jamey@minilop.net>

* Update cranelift/codegen/src/machinst/abi.rs

Co-authored-by: Jamey Sharp <jamey@minilop.net>

* Fix offsets

* Add comment

Co-authored-by: Jamey Sharp <jamey@minilop.net>
This commit is contained in:
Timothy Chen
2022-11-30 07:19:41 -08:00
committed by GitHub
parent 2bb1fb08fa
commit 67fc5389b0
3 changed files with 66 additions and 59 deletions
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4
cranelift/codegen/src/isa/s390x/lower/isle.rs
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@@ -126,7 +126,7 @@ impl generated_code::Context for IsleContext<'_, '_, MInst, Flags, IsaFlags, 6>
fn defs_init(&mut self, abi: &Sig) -> CallRetList {
// Allocate writable registers for all retval regs, except for StructRet args.
let mut defs = smallvec![];
for i in 0..self.lower_ctx.sigs()[*abi].num_rets() {
for i in 0..self.lower_ctx.sigs().num_rets(*abi) {
if let &ABIArg::Slots {
ref slots, purpose, ..
} = &self.lower_ctx.sigs().get_ret(*abi, i)
@@ -169,7 +169,7 @@ impl generated_code::Context for IsleContext<'_, '_, MInst, Flags, IsaFlags, 6>
// Return the index of the first actual return value, excluding
// any StructReturn that might have been added to Sig.
let sig = &self.lower_ctx.dfg().signatures[sig_ref];
self.lower_ctx.sigs()[*abi].num_rets() - sig.returns.len()
self.lower_ctx.sigs().num_rets(*abi) - sig.returns.len()
}
fn abi_lane_order(&mut self, abi: &Sig) -> LaneOrder {