s390x: Support both big- and little-endian vector lane order (#4682)
This implements the s390x back-end portion of the solution for https://github.com/bytecodealliance/wasmtime/issues/4566 We now support both big- and little-endian vector lane order in code generation. The order used for a function is determined by the function's ABI: if it uses a Wasmtime ABI, it will use little-endian lane order, and big-endian lane order otherwise. (This ensures that all raw_bitcast instructions generated by both wasmtime and other cranelift frontends can always be implemented as a no-op.) Lane order affects the implementation of a number of operations: - Vector immediates - Vector memory load / store (in big- and little-endian variants) - Operations explicitly using lane numbers (insertlane, extractlane, shuffle, swizzle) - Operations implicitly using lane numbers (iadd_pairwise, narrow/widen, promote/demote, fcvt_low, vhigh_bits) In addition, when calling a function using a different lane order, we need to lane-swap all vector values passed or returned in registers. A small number of changes to common code were also needed: - Ensure we always select a Wasmtime calling convention on s390x in crates/cranelift (func_signature). - Fix vector immediates for filetests/runtests. In PR #4427, I attempted to fix this by byte-swapping the V128 value, but with the new scheme, we'd instead need to perform a per-lane byte swap. Since we do not know the actual type in write_to_slice and read_from_slice, this isn't easily possible. Revert this part of PR #4427 again, and instead just mark the memory buffer as little-endian when emitting the trampoline; the back-end will then emit correct code to load the constant. - Change a runtest in simd-bitselect-to-vselect.clif to no longer make little-endian lane order assumptions. - Remove runtests in simd-swizzle.clif that make little-endian lane order assumptions by relying on implicit type conversion when using a non-i16x8 swizzle result type (this feature should probably be removed anyway). Tested with both wasmtime and cg_clif.
This commit is contained in:
Ulrich Weigand
@@ -28,8 +28,9 @@ mod emit_tests;
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// Instructions (top level): definition
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pub use crate::isa::s390x::lower::isle::generated_code::{
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ALUOp, CmpOp, FPUOp1, FPUOp2, FPUOp3, FpuRoundMode, FpuRoundOp, MInst as Inst, RxSBGOp,
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ShiftOp, SymbolReloc, UnaryOp, VecBinaryOp, VecFloatCmpOp, VecIntCmpOp, VecShiftOp, VecUnaryOp,
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ALUOp, CmpOp, FPUOp1, FPUOp2, FPUOp3, FpuRoundMode, FpuRoundOp, LaneOrder, MInst as Inst,
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RxSBGOp, ShiftOp, SymbolReloc, UnaryOp, VecBinaryOp, VecFloatCmpOp, VecIntCmpOp, VecShiftOp,
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VecUnaryOp,
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};
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/// Additional information for (direct) Call instructions, left out of line to lower the size of
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@@ -245,7 +246,19 @@ impl Inst {
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// These are all part of VXRS_EXT2
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Inst::VecLoadRev { .. }
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| Inst::VecLoadByte16Rev { .. }
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| Inst::VecLoadByte32Rev { .. }
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| Inst::VecLoadByte64Rev { .. }
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| Inst::VecLoadElt16Rev { .. }
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| Inst::VecLoadElt32Rev { .. }
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| Inst::VecLoadElt64Rev { .. }
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| Inst::VecStoreRev { .. }
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| Inst::VecStoreByte16Rev { .. }
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| Inst::VecStoreByte32Rev { .. }
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| Inst::VecStoreByte64Rev { .. }
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| Inst::VecStoreElt16Rev { .. }
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| Inst::VecStoreElt32Rev { .. }
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| Inst::VecStoreElt64Rev { .. }
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| Inst::VecLoadReplicateRev { .. }
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| Inst::VecLoadLaneRev { .. }
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| Inst::VecLoadLaneRevUndef { .. }
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@@ -762,6 +775,30 @@ fn s390x_get_operands<F: Fn(VReg) -> VReg>(inst: &Inst, collector: &mut OperandC
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collector.reg_def(rd);
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memarg_operands(mem, collector);
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}
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&Inst::VecLoadByte16Rev { rd, ref mem, .. } => {
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collector.reg_def(rd);
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memarg_operands(mem, collector);
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}
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&Inst::VecLoadByte32Rev { rd, ref mem, .. } => {
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collector.reg_def(rd);
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memarg_operands(mem, collector);
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}
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&Inst::VecLoadByte64Rev { rd, ref mem, .. } => {
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collector.reg_def(rd);
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memarg_operands(mem, collector);
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}
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&Inst::VecLoadElt16Rev { rd, ref mem, .. } => {
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collector.reg_def(rd);
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memarg_operands(mem, collector);
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}
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&Inst::VecLoadElt32Rev { rd, ref mem, .. } => {
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collector.reg_def(rd);
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memarg_operands(mem, collector);
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}
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&Inst::VecLoadElt64Rev { rd, ref mem, .. } => {
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collector.reg_def(rd);
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memarg_operands(mem, collector);
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}
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&Inst::VecStore { rd, ref mem, .. } => {
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collector.reg_use(rd);
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memarg_operands(mem, collector);
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@@ -770,6 +807,30 @@ fn s390x_get_operands<F: Fn(VReg) -> VReg>(inst: &Inst, collector: &mut OperandC
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collector.reg_use(rd);
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memarg_operands(mem, collector);
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}
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&Inst::VecStoreByte16Rev { rd, ref mem, .. } => {
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collector.reg_use(rd);
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memarg_operands(mem, collector);
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}
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&Inst::VecStoreByte32Rev { rd, ref mem, .. } => {
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collector.reg_use(rd);
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memarg_operands(mem, collector);
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}
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&Inst::VecStoreByte64Rev { rd, ref mem, .. } => {
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collector.reg_use(rd);
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memarg_operands(mem, collector);
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}
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&Inst::VecStoreElt16Rev { rd, ref mem, .. } => {
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collector.reg_use(rd);
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memarg_operands(mem, collector);
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}
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&Inst::VecStoreElt32Rev { rd, ref mem, .. } => {
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collector.reg_use(rd);
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memarg_operands(mem, collector);
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}
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&Inst::VecStoreElt64Rev { rd, ref mem, .. } => {
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collector.reg_use(rd);
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memarg_operands(mem, collector);
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}
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&Inst::VecLoadReplicate { rd, ref mem, .. } => {
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collector.reg_def(rd);
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memarg_operands(mem, collector);
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@@ -2476,10 +2537,23 @@ impl Inst {
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op, rm, rn, tmp, rn, rm
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)
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}
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&Inst::VecLoad { rd, ref mem } | &Inst::VecLoadRev { rd, ref mem } => {
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&Inst::VecLoad { rd, ref mem }
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| &Inst::VecLoadRev { rd, ref mem }
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| &Inst::VecLoadByte16Rev { rd, ref mem }
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| &Inst::VecLoadByte32Rev { rd, ref mem }
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| &Inst::VecLoadByte64Rev { rd, ref mem }
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| &Inst::VecLoadElt16Rev { rd, ref mem }
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| &Inst::VecLoadElt32Rev { rd, ref mem }
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| &Inst::VecLoadElt64Rev { rd, ref mem } => {
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let opcode = match self {
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&Inst::VecLoad { .. } => "vl",
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&Inst::VecLoadRev { .. } => "vlbrq",
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&Inst::VecLoadByte16Rev { .. } => "vlbrh",
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&Inst::VecLoadByte32Rev { .. } => "vlbrf",
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&Inst::VecLoadByte64Rev { .. } => "vlbrg",
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&Inst::VecLoadElt16Rev { .. } => "vlerh",
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&Inst::VecLoadElt32Rev { .. } => "vlerf",
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&Inst::VecLoadElt64Rev { .. } => "vlerg",
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_ => unreachable!(),
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};
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@@ -2489,10 +2563,23 @@ impl Inst {
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let mem = mem.pretty_print_default();
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format!("{}{} {}, {}", mem_str, opcode, rd, mem)
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}
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&Inst::VecStore { rd, ref mem } | &Inst::VecStoreRev { rd, ref mem } => {
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&Inst::VecStore { rd, ref mem }
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| &Inst::VecStoreRev { rd, ref mem }
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| &Inst::VecStoreByte16Rev { rd, ref mem }
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| &Inst::VecStoreByte32Rev { rd, ref mem }
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| &Inst::VecStoreByte64Rev { rd, ref mem }
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| &Inst::VecStoreElt16Rev { rd, ref mem }
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| &Inst::VecStoreElt32Rev { rd, ref mem }
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| &Inst::VecStoreElt64Rev { rd, ref mem } => {
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let opcode = match self {
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&Inst::VecStore { .. } => "vst",
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&Inst::VecStoreRev { .. } => "vstbrq",
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&Inst::VecStoreByte16Rev { .. } => "vstbrh",
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&Inst::VecStoreByte32Rev { .. } => "vstbrf",
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&Inst::VecStoreByte64Rev { .. } => "vstbrg",
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&Inst::VecStoreElt16Rev { .. } => "vsterh",
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&Inst::VecStoreElt32Rev { .. } => "vsterf",
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&Inst::VecStoreElt64Rev { .. } => "vsterg",
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_ => unreachable!(),
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};
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