Fix for #141 (#142)

* Add Atom and Literal base classes to CDSL Ast. Change substitution() and copy() on Def/Apply/Rtl to support substituting Var->Union[Var, Literal]. Check in Apply() constructor kinds of passed in Literals respect instruction signature

* Change verify_semantics to check all possible instantiations of enumerated immediates (needed to descrive icmp). Add all bitvector comparison primitives and bvite; Change set_semantics to optionally accept XForms; Add semantics for icmp; Fix typing errors in semantics/{smtlib, elaborate, __init__}.py after the change of VarMap->VarAtomMap

* Forgot macros.py

* Nit obscured by testing with mypy enabled present.

* Typo

lib/cretonne/meta/semantics/test_elaborate.py

@@ -1,7 +1,7 @@
 from __future__ import absolute_import
 from base.instructions import vselect, vsplit, vconcat, iconst, iadd, bint
 from base.instructions import b1, icmp, ireduce, iadd_cout
-from base.immediates import intcc
+from base.immediates import intcc, imm64
 from base.types import i64, i8, b32, i32, i16, f32
 from cdsl.typevar import TypeVar
 from cdsl.ast import Var
@@ -9,7 +9,7 @@ from cdsl.xform import Rtl
 from unittest import TestCase
 from .elaborate import elaborate
 from .primitives import prim_to_bv, bvsplit, prim_from_bv, bvconcat, bvadd, \
-    bvult
+    bvult, bv_from_imm64, bvite
 import base.semantics  # noqa
 
 
@@ -366,9 +366,12 @@ class TestElaborate(TestCase):
         a = Var('a')
         c_out = Var('c_out')
         bvc_out = Var('bvc_out')
+        bc_out = Var('bc_out')
         bvx = Var('bvx')
         bvy = Var('bvy')
         bva = Var('bva')
+        bvone = Var('bvone')
+        bvzero = Var('bvzero')
         r = Rtl(
                 (a, c_out) << iadd_cout.i32(x, y),
         )
@@ -378,10 +381,12 @@ class TestElaborate(TestCase):
             bvx << prim_to_bv.i32(x),
             bvy << prim_to_bv.i32(y),
             bva << bvadd.bv32(bvx, bvy),
-            bvc_out << bvult.bv32(bva, bvx),
+            bc_out << bvult.bv32(bva, bvx),
+            bvone << bv_from_imm64(imm64(1)),
+            bvzero << bv_from_imm64(imm64(0)),
+            bvc_out << bvite(bc_out, bvone, bvzero),
             a << prim_from_bv.i32(bva),
             c_out << prim_from_bv.b1(bvc_out)
         )
         exp.cleanup_concrete_rtl()
-
         assert concrete_rtls_eq(sem, exp)