From 66d2c0a95af604425575f8bbac317d5fe2856e79 Mon Sep 17 00:00:00 2001
From: Jakob Stoklund Olesen <jolesen@mozilla.com>
Date: Mon, 15 May 2017 16:01:24 -0700
Subject: [PATCH] Add a RegClassMask typedef and a MAX_TOPRCS constant.

Avoid spreading u32 as a bitmask of register classes throughout the
code.

Enforce the limit of 32 register classes total. This could easily be
raised if needed.

The MAX_TOPRCS constant is the highest possible number of top-level
register classes in an ISA. The RegClassData.toprc field is always
smaller than this limit.
---
 lib/cretonne/meta/cdsl/isa.py     | 10 ++++++++++
 lib/cretonne/src/isa/registers.rs | 14 +++++++++++++-
 2 files changed, 23 insertions(+), 1 deletion(-)

diff --git a/lib/cretonne/meta/cdsl/isa.py b/lib/cretonne/meta/cdsl/isa.py
index 9239bf2f70..a2387bc0ff 100644
--- a/lib/cretonne/meta/cdsl/isa.py
+++ b/lib/cretonne/meta/cdsl/isa.py
@@ -119,6 +119,11 @@ class TargetISA(object):
             bank.finish_regclasses()
             self.regclasses.extend(bank.toprcs)
 
+        # The limit on the number of top-level register classes can be raised.
+        # This should be coordinated with the `MAX_TOPRCS` constant in
+        # `isa/registers.rs`.
+        assert len(self.regclasses) <= 4, "Too many top-level register classes"
+
         # Collect all of the non-top-level register classes.
         # They are numbered strictly after the top-level classes.
         for bank in self.regbanks:
@@ -128,6 +133,11 @@ class TargetISA(object):
         for idx, rc in enumerate(self.regclasses):
             rc.index = idx
 
+        # The limit on the number of register classes can be changed. It should
+        # be coordinated with the `RegClassMask` and `RegClassIndex` types in
+        # `isa/registers.rs`.
+        assert len(self.regclasses) <= 32, "Too many register classes"
+
 
 class CPUMode(object):
     """
diff --git a/lib/cretonne/src/isa/registers.rs b/lib/cretonne/src/isa/registers.rs
index a4527733c5..5549e98157 100644
--- a/lib/cretonne/src/isa/registers.rs
+++ b/lib/cretonne/src/isa/registers.rs
@@ -20,6 +20,18 @@ pub type RegUnit = u16;
 /// This type should be coordinated with meta/cdsl/registers.py.
 pub type RegUnitMask = [u32; 3];
 
+/// A bit mask indexed by register classes.
+///
+/// The size of this type is determined by the ISA with the most register classes.
+///
+/// This type should be coordinated with meta/cdsl/isa.py.
+pub type RegClassMask = u32;
+
+/// Guaranteed maximum number of top-level register classes in any ISA.
+///
+/// This can be increased, but should be coordinated with meta/cdsl/isa.py.
+pub const MAX_TOPRCS: usize = 4;
+
 /// The register units in a target ISA are divided into disjoint register banks. Each bank covers a
 /// contiguous range of register units.
 ///
@@ -129,7 +141,7 @@ pub struct RegClassData {
     /// Bit-mask of sub-classes of this register class, including itself.
     ///
     /// Bits correspond to RC indexes.
-    pub subclasses: u32,
+    pub subclasses: RegClassMask,
 
     /// Mask of register units in the class. If `width > 1`, the mask only has a bit set for the
     /// first register unit in each allocatable register.