From 6609d7baf4e8f19e4dfb5099b3a42ebe3d83b2c9 Mon Sep 17 00:00:00 2001
From: Jakob Stoklund Olesen <jolesen@mozilla.com>
Date: Fri, 28 Jul 2017 16:13:51 -0700
Subject: [PATCH] Try to depend only on the `ir` module being in scope.

Generated code should used qualified names assuming that `ir` is in
scope, not everything else.
---
 lib/cretonne/meta/cdsl/types.py          | 2 +-
 lib/cretonne/meta/gen_encoding.py        | 6 +++---
 lib/cretonne/meta/gen_instr.py           | 4 ++--
 lib/cretonne/src/ir/instructions.rs      | 1 +
 lib/cretonne/src/isa/arm32/enc_tables.rs | 2 +-
 lib/cretonne/src/isa/arm64/enc_tables.rs | 2 +-
 lib/cretonne/src/isa/intel/enc_tables.rs | 2 +-
 lib/cretonne/src/isa/riscv/enc_tables.rs | 2 +-
 lib/cretonne/src/legalizer/mod.rs        | 1 -
 9 files changed, 11 insertions(+), 11 deletions(-)

diff --git a/lib/cretonne/meta/cdsl/types.py b/lib/cretonne/meta/cdsl/types.py
index 53a1dd79ad..8ae66ee359 100644
--- a/lib/cretonne/meta/cdsl/types.py
+++ b/lib/cretonne/meta/cdsl/types.py
@@ -39,7 +39,7 @@ class ValueType(object):
 
     def rust_name(self):
         # type: () -> str
-        return 'types::' + self.name.upper()
+        return 'ir::types::' + self.name.upper()
 
     @staticmethod
     def by_name(name):
diff --git a/lib/cretonne/meta/gen_encoding.py b/lib/cretonne/meta/gen_encoding.py
index c3b3ddb87c..0516b5c4c8 100644
--- a/lib/cretonne/meta/gen_encoding.py
+++ b/lib/cretonne/meta/gen_encoding.py
@@ -653,7 +653,7 @@ def emit_level2_hashtables(level2_hashtables, offt, level2_doc, fmt):
             if entry:
                 fmt.line(
                         'Level2Entry ' +
-                        '{{ opcode: Some(Opcode::{}), offset: {:#08x} }},'
+                        '{{ opcode: Some(ir::Opcode::{}), offset: {:#08x} }},'
                         .format(entry.inst.camel_name, entry.offset))
             else:
                 fmt.line(
@@ -678,7 +678,7 @@ def emit_level1_hashtable(cpumode, level1, offt, fmt):
             # Empty hash table entry. Include the default legalization action.
             if not level2:
                 fmt.format(
-                        'Level1Entry {{ ty: types::VOID, log2len: !0, '
+                        'Level1Entry {{ ty: ir::types::VOID, log2len: !0, '
                         'offset: 0, legalize: {} }},',
                         level1.legalize_code)
                 continue
@@ -686,7 +686,7 @@ def emit_level1_hashtable(cpumode, level1, offt, fmt):
             if level2.ty is not None:
                 tyname = level2.ty.rust_name()
             else:
-                tyname = 'types::VOID'
+                tyname = 'ir::types::VOID'
 
             lcode = cpumode.isa.legalize_code(level2.legalize)
 
diff --git a/lib/cretonne/meta/gen_instr.py b/lib/cretonne/meta/gen_instr.py
index b0c9943806..ade66e643c 100644
--- a/lib/cretonne/meta/gen_instr.py
+++ b/lib/cretonne/meta/gen_instr.py
@@ -350,10 +350,10 @@ def gen_typesets_table(fmt, type_sets):
     fmt.comment('Table of value type sets.')
     assert len(type_sets.table) <= typeset_limit, "Too many type sets"
     with fmt.indented(
-            'const TYPE_SETS : [ValueTypeSet; {}] = ['
+            'const TYPE_SETS : [ir::instructions::ValueTypeSet; {}] = ['
             .format(len(type_sets.table)), '];'):
         for ts in type_sets.table:
-            with fmt.indented('ValueTypeSet {', '},'):
+            with fmt.indented('ir::instructions::ValueTypeSet {', '},'):
                 ts.emit_fields(fmt)
 
 
diff --git a/lib/cretonne/src/ir/instructions.rs b/lib/cretonne/src/ir/instructions.rs
index 279a7a37a9..900dd56e88 100644
--- a/lib/cretonne/src/ir/instructions.rs
+++ b/lib/cretonne/src/ir/instructions.rs
@@ -10,6 +10,7 @@ use std::fmt::{self, Display, Formatter};
 use std::str::FromStr;
 use std::ops::{Deref, DerefMut};
 
+use ir;
 use ir::{Value, Type, Ebb, JumpTable, SigRef, FuncRef, StackSlot, MemFlags};
 use ir::immediates::{Imm64, Uimm8, Ieee32, Ieee64, Offset32, Uoffset32};
 use ir::condcodes::*;
diff --git a/lib/cretonne/src/isa/arm32/enc_tables.rs b/lib/cretonne/src/isa/arm32/enc_tables.rs
index eeb8466669..f71dd33f87 100644
--- a/lib/cretonne/src/isa/arm32/enc_tables.rs
+++ b/lib/cretonne/src/isa/arm32/enc_tables.rs
@@ -1,6 +1,6 @@
 //! Encoding tables for ARM32 ISA.
 
-use ir::types;
+use ir;
 use isa;
 use isa::constraints::*;
 use isa::enc_tables::*;
diff --git a/lib/cretonne/src/isa/arm64/enc_tables.rs b/lib/cretonne/src/isa/arm64/enc_tables.rs
index c2c087e039..6007450cb5 100644
--- a/lib/cretonne/src/isa/arm64/enc_tables.rs
+++ b/lib/cretonne/src/isa/arm64/enc_tables.rs
@@ -1,6 +1,6 @@
 //! Encoding tables for ARM64 ISA.
 
-use ir::types;
+use ir;
 use isa;
 use isa::constraints::*;
 use isa::enc_tables::*;
diff --git a/lib/cretonne/src/isa/intel/enc_tables.rs b/lib/cretonne/src/isa/intel/enc_tables.rs
index 62ef7b3cd6..ad66cb1f7f 100644
--- a/lib/cretonne/src/isa/intel/enc_tables.rs
+++ b/lib/cretonne/src/isa/intel/enc_tables.rs
@@ -1,6 +1,6 @@
 //! Encoding tables for Intel ISAs.
 
-use ir::{self, types, Opcode};
+use ir;
 use isa;
 use isa::constraints::*;
 use isa::enc_tables::*;
diff --git a/lib/cretonne/src/isa/riscv/enc_tables.rs b/lib/cretonne/src/isa/riscv/enc_tables.rs
index 0d11d006c5..f095e67243 100644
--- a/lib/cretonne/src/isa/riscv/enc_tables.rs
+++ b/lib/cretonne/src/isa/riscv/enc_tables.rs
@@ -1,7 +1,7 @@
 //! Encoding tables for RISC-V.
 
 use ir::condcodes::IntCC;
-use ir::{self, types, Opcode};
+use ir;
 use isa;
 use isa::constraints::*;
 use isa::enc_tables::*;
diff --git a/lib/cretonne/src/legalizer/mod.rs b/lib/cretonne/src/legalizer/mod.rs
index c5178a97ee..c6a844c3c1 100644
--- a/lib/cretonne/src/legalizer/mod.rs
+++ b/lib/cretonne/src/legalizer/mod.rs
@@ -19,7 +19,6 @@ use ir::{self, Function, Cursor};
 use ir::condcodes::IntCC;
 use isa::TargetIsa;
 use bitset::BitSet;
-use ir::instructions::ValueTypeSet;
 
 mod boundary;
 mod split;