Add x86 SIMD ishl

Only the shifts with applicable SSE2 instructions (i.e. 16-64 bit width) are implemented here.

cranelift/filetests/filetests/isa/x86/simd-bitwise-binemit.clif

@@ -0,0 +1,21 @@
+test binemit
+set enable_simd
+target x86_64 skylake
+
+function %ishl_i16x8(i16x8, i64x2) -> i16x8 {
+ebb0(v0: i16x8 [%xmm2], v1: i64x2 [%xmm1]):
+[-, %xmm2]  v2 = x86_psll v0, v1     ; bin: 66 0f f1 d1
+            return v2
+}
+
+function %ishl_i32x4(i32x4, i64x2) -> i32x4 {
+ebb0(v0: i32x4 [%xmm4], v1: i64x2 [%xmm0]):
+[-, %xmm4]  v2 = x86_psll v0, v1      ; bin: 66 0f f2 e0
+            return v2
+}
+
+function %ishl_i64x2(i64x2, i64x2) -> i64x2 {
+ebb0(v0: i64x2 [%xmm6], v1: i64x2 [%xmm3]):
+[-, %xmm6]  v2 = x86_psll v0, v1      ; bin: 66 0f f3 f3
+            return v2
+}

cranelift/filetests/filetests/isa/x86/simd-bitwise-legalize.clif

@@ -0,0 +1,13 @@
+test legalizer
+set enable_simd
+target x86_64 skylake
+
+function %ishl_i32x4() -> i32x4 {
+ebb0:
+    v0 = iconst.i32 1
+    v1 = vconst.i32x4 [1 2 4 8]
+    v2 = ishl v1, v0
+    ; check: v3 = bitcast.i64x2 v0
+    ; nextln: v2 = x86_psll v1, v3
+    return v2
+}

cranelift/filetests/filetests/isa/x86/simd-bitwise-run.clif

@@ -0,0 +1,39 @@
+test run
+set enable_simd
+target x86_64 skylake
+
+; TODO: once available, replace all lane extraction with `icmp + all_ones`
+
+function %ishl_i32x4() -> b1 {
+ebb0:
+    v0 = iconst.i32 1
+    v1 = vconst.i32x4 [1 2 4 8]
+    v2 = ishl v1, v0
+
+    v3 = extractlane v2, 0
+    v4 = icmp_imm eq v3, 2
+
+    v5 = extractlane v2, 3
+    v6 = icmp_imm eq v5, 16
+
+    v7 = band v4, v6
+    return v7
+}
+; run
+
+function %ishl_too_large_i16x8() -> b1 {
+ebb0:
+    v0 = iconst.i32 17 ; note that this will shift off the end of each lane
+    v1 = vconst.i16x8 [1 2 4 8 16 32 64 128]
+    v2 = ishl v1, v0
+
+    v3 = extractlane v2, 0
+    v4 = icmp_imm eq v3, 0
+
+    v5 = extractlane v2, 3
+    v6 = icmp_imm eq v5, 0
+
+    v7 = band v4, v6
+    return v7
+}
+; run