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Merge pull request from GHSA-ff4p-7xrq-q5r8

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* x64: Remove incorrect `amode_add` lowering rules

This commit removes two incorrect rules as part of the x64 backend's
computation of addressing modes. These two rules folded a zero-extended
32-bit computation into the address mode operand, but this isn't correct
as the 32-bit computation should be truncated to 32-bits but when folded
into the address mode computation it happens with 64-bit operands,
meaning truncation doesn't happen.

* Add release notes
This commit is contained in:
Alex Crichton
2023-03-08 13:00:40 -06:00
committed by GitHub
parent 5dc2bbccbb
commit 63fb30e4b4
3 changed files with 52 additions and 20 deletions
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14
cranelift/codegen/src/isa/x64/inst.isle
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@@ -1063,20 +1063,6 @@
(rule 2 (amode_add (Amode.ImmReg off (valid_reg base) flags) (ishl index (iconst (uimm8 shift))))
(if (u32_lteq (u8_as_u32 shift) 3))
(Amode.ImmRegRegShift off base index shift flags))
(rule 2 (amode_add (Amode.ImmReg off (valid_reg base) flags) (uextend (ishl index (iconst (uimm8 shift)))))
(if (u32_lteq (u8_as_u32 shift) 3))
(Amode.ImmRegRegShift off base (extend_to_gpr index $I64 (ExtendKind.Zero)) shift flags))
;; Same, but with a uextend of a shift of a 32-bit add. This is valid
;; because we know our lowering of a narrower-than-64-bit `iadd` will
;; always write the full register width, so we can effectively ignore
;; the `uextend` and look through it to the `ishl`.
;;
;; Priority 3 to avoid conflict with the previous rule.
(rule 3 (amode_add (Amode.ImmReg off (valid_reg base) flags)
(uextend (ishl index @ (iadd _ _) (iconst (uimm8 shift)))))
(if (u32_lteq (u8_as_u32 shift) 3))
(Amode.ImmRegRegShift off base index shift flags))
;; -- Case 4 (absorbing constant offsets).
;;