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arm64: Implement basic SIMD arithmetic

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Copyright (c) 2020, Arm Limited.
This commit is contained in:
Joey Gouly
2020-07-02 13:17:33 +01:00
parent 8e257e731e
commit 62e7b7f838
5 changed files with 277 additions and 30 deletions
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176
cranelift/codegen/src/isa/aarch64/inst/emit_tests.rs
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@@ -2341,6 +2341,138 @@ fn test_aarch64_binemit() {
"umaxp v1.4s, v20.4s, v16.4s",
));
insns.push((
Inst::VecRRR {
alu_op: VecALUOp::Add,
rd: writable_vreg(5),
rn: vreg(1),
rm: vreg(1),
ty: I8X16,
},
"2584214E",
"add v5.16b, v1.16b, v1.16b",
));
insns.push((
Inst::VecRRR {
alu_op: VecALUOp::Add,
rd: writable_vreg(7),
rn: vreg(13),
rm: vreg(2),
ty: I16X8,
},
"A785624E",
"add v7.8h, v13.8h, v2.8h",
));
insns.push((
Inst::VecRRR {
alu_op: VecALUOp::Add,
rd: writable_vreg(18),
rn: vreg(9),
rm: vreg(6),
ty: I32X4,
},
"3285A64E",
"add v18.4s, v9.4s, v6.4s",
));
insns.push((
Inst::VecRRR {
alu_op: VecALUOp::Add,
rd: writable_vreg(1),
rn: vreg(3),
rm: vreg(2),
ty: I64X2,
},
"6184E24E",
"add v1.2d, v3.2d, v2.2d",
));
insns.push((
Inst::VecRRR {
alu_op: VecALUOp::Sub,
rd: writable_vreg(5),
rn: vreg(1),
rm: vreg(1),
ty: I8X16,
},
"2584216E",
"sub v5.16b, v1.16b, v1.16b",
));
insns.push((
Inst::VecRRR {
alu_op: VecALUOp::Sub,
rd: writable_vreg(7),
rn: vreg(13),
rm: vreg(2),
ty: I16X8,
},
"A785626E",
"sub v7.8h, v13.8h, v2.8h",
));
insns.push((
Inst::VecRRR {
alu_op: VecALUOp::Sub,
rd: writable_vreg(18),
rn: vreg(9),
rm: vreg(6),
ty: I32X4,
},
"3285A66E",
"sub v18.4s, v9.4s, v6.4s",
));
insns.push((
Inst::VecRRR {
alu_op: VecALUOp::Sub,
rd: writable_vreg(18),
rn: vreg(0),
rm: vreg(8),
ty: I64X2,
},
"1284E86E",
"sub v18.2d, v0.2d, v8.2d",
));
insns.push((
Inst::VecRRR {
alu_op: VecALUOp::Mul,
rd: writable_vreg(25),
rn: vreg(9),
rm: vreg(8),
ty: I8X16,
},
"399D284E",
"mul v25.16b, v9.16b, v8.16b",
));
insns.push((
Inst::VecRRR {
alu_op: VecALUOp::Mul,
rd: writable_vreg(30),
rn: vreg(30),
rm: vreg(12),
ty: I16X8,
},
"DE9F6C4E",
"mul v30.8h, v30.8h, v12.8h",
));
insns.push((
Inst::VecRRR {
alu_op: VecALUOp::Mul,
rd: writable_vreg(18),
rn: vreg(18),
rm: vreg(18),
ty: I32X4,
},
"529EB24E",
"mul v18.4s, v18.4s, v18.4s",
));
insns.push((
Inst::VecMisc {
op: VecMisc2::Not,
@@ -2352,6 +2484,50 @@ fn test_aarch64_binemit() {
"mvn v2.16b, v1.16b",
));
insns.push((
Inst::VecMisc {
op: VecMisc2::Neg,
rd: writable_vreg(8),
rn: vreg(12),
ty: I8X16,
},
"88B9206E",
"neg v8.16b, v12.16b",
));
insns.push((
Inst::VecMisc {
op: VecMisc2::Neg,
rd: writable_vreg(0),
rn: vreg(31),
ty: I16X8,
},
"E0BB606E",
"neg v0.8h, v31.8h",
));
insns.push((
Inst::VecMisc {
op: VecMisc2::Neg,
rd: writable_vreg(2),
rn: vreg(3),
ty: I32X4,
},
"62B8A06E",
"neg v2.4s, v3.4s",
));
insns.push((
Inst::VecMisc {
op: VecMisc2::Neg,
rd: writable_vreg(10),
rn: vreg(8),
ty: I64X2,
},
"0AB9E06E",
"neg v10.2d, v8.2d",
));
insns.push((
Inst::VecLanes {
op: VecLanesOp::Uminv,