AArch64: make use of reg-reg-extend amode.

When a load/store instruction needs an address of the form `v0 +
uextend(v1)` or `v0 + sextend(v1)` (or the commuted forms thereof), we
currently generate a separate zero/sign-extend operation and then use a
plain `[rA, rB]` addressing mode. This patch extends `lower_address()`
to look at both addends of an address if it has two addends and a zero
offset, recognize extension operations, and incorporate them directly
into a `[rA, rB, UXTW]` or `[rA, rB, SXTW]` form. This should improve
our performence on WebAssembly workloads, at least, because we often see
a 64-bit linear memory base indexed by a 32-bit (Wasm) pointer value.

cranelift/codegen/src/isa/aarch64/inst/args.rs

@@ -133,6 +133,9 @@ pub enum MemArg {
     /// first.
     RegScaledExtended(Reg, Reg, Type, ExtendOp),
 
+    /// Register plus register offset, with index sign- or zero-extended first.
+    RegExtended(Reg, Reg, ExtendOp),
+
     /// Unscaled signed 9-bit immediate offset from reg.
     Unscaled(Reg, SImm9),
 
@@ -412,6 +415,19 @@ impl ShowWithRRU for MemArg {
                     shift
                 )
             }
+            &MemArg::RegExtended(r1, r2, op) => {
+                let size = match op {
+                    ExtendOp::SXTW | ExtendOp::UXTW => InstSize::Size32,
+                    _ => InstSize::Size64,
+                };
+                let op = op.show_rru(mb_rru);
+                format!(
+                    "[{}, {}, {}]",
+                    r1.show_rru(mb_rru),
+                    show_ireg_sized(r2, mb_rru, size),
+                    op,
+                )
+            }
             &MemArg::Label(ref label) => label.show_rru(mb_rru),
             &MemArg::PreIndexed(r, simm9) => format!(
                 "[{}, {}]!",