diff --git a/filetests/isa/riscv/legalize-abi.cton b/filetests/isa/riscv/legalize-abi.cton
index 06fcfd5f6c..2e7da079bf 100644
--- a/filetests/isa/riscv/legalize-abi.cton
+++ b/filetests/isa/riscv/legalize-abi.cton
@@ -96,7 +96,7 @@ ebb0(v0: i64x4):
     ; check: $(v0d=$V) = iconcat $v0dl, $v0dh
     ; check: $(v0cd=$V) = vconcat $v0c, $v0d
     ; check: $(v0abcd=$V) = vconcat $v0ab, $v0cd
-    v1 = iadd v0, v0
+    v1 = bxor v0, v0
     ; check: $(v1ab=$V), $(v1cd=$V) = vsplit
     ; check: $(v1a=$V), $(v1b=$V) = vsplit $v1ab
     ; check: $(v1al=$V), $(v1ah=$V) = isplit $v1a
diff --git a/filetests/isa/riscv/legalize-i64.cton b/filetests/isa/riscv/legalize-i64.cton
index dfa78447af..e2d5a763a2 100644
--- a/filetests/isa/riscv/legalize-i64.cton
+++ b/filetests/isa/riscv/legalize-i64.cton
@@ -57,8 +57,8 @@ ebb0(v1: i64, v2: i64):
 ; check: $(c=$V) = icmp ult, $v3l, $v1l
 ; check: [R#0c
 ; sameln: $(v3h1=$V) = iadd $v1h, $v2h
-; TODO: This doesn't typecheck. We need to convert the b1 result to i32.
+; check: $(c_int=$V) = bint.i32 $c
 ; check: [R#0c
-; sameln: $(v3h=$V) = iadd $v3h1, $c
+; sameln: $(v3h=$V) = iadd $v3h1, $c_int
 ; check: $v3 = iconcat $v3l, $v3h
 ; check: return $v3l, $v3h
diff --git a/lib/cretonne/meta/base/legalize.py b/lib/cretonne/meta/base/legalize.py
index 9b0def9ae9..dc8185daf2 100644
--- a/lib/cretonne/meta/base/legalize.py
+++ b/lib/cretonne/meta/base/legalize.py
@@ -10,7 +10,7 @@ from __future__ import absolute_import
 from .instructions import iadd, iadd_cout, iadd_cin, iadd_carry, iadd_imm
 from .instructions import isub, isub_bin, isub_bout, isub_borrow
 from .instructions import band, bor, bxor, isplit, iconcat
-from .instructions import icmp, iconst
+from .instructions import icmp, iconst, bint
 from cdsl.ast import Var
 from cdsl.xform import Rtl, XFormGroup
 
@@ -40,10 +40,12 @@ b = Var('b')
 b1 = Var('b1')
 b2 = Var('b2')
 b_in = Var('b_in')
+b_int = Var('b_int')
 c = Var('c')
 c1 = Var('c1')
 c2 = Var('c2')
 c_in = Var('c_in')
+c_int = Var('c_int')
 xl = Var('xl')
 xh = Var('xh')
 yl = Var('yl')
@@ -102,21 +104,24 @@ expand.legalize(
         a << iadd_cin(x, y, c),
         Rtl(
             a1 << iadd(x, y),
-            a << iadd(a1, c)
+            c_int << bint(c),
+            a << iadd(a1, c_int)
         ))
 
 expand.legalize(
         a << isub_bin(x, y, b),
         Rtl(
             a1 << isub(x, y),
-            a << isub(a1, b)
+            b_int << bint(b),
+            a << isub(a1, b_int)
         ))
 
 expand.legalize(
         (a, c) << iadd_carry(x, y, c_in),
         Rtl(
             (a1, c1) << iadd_cout(x, y),
-            (a, c2) << iadd_cout(a1, c_in),
+            c_int << bint(c_in),
+            (a, c2) << iadd_cout(a1, c_int),
             c << bor(c1, c2)
         ))
 
@@ -124,7 +129,8 @@ expand.legalize(
         (a, b) << isub_borrow(x, y, b_in),
         Rtl(
             (a1, b1) << isub_bout(x, y),
-            (a, b2) << isub_bout(a1, b_in),
+            b_int << bint(b_in),
+            (a, b2) << isub_bout(a1, b_int),
             b << bor(b1, b2)
         ))
 
diff --git a/lib/cretonne/src/isa/enc_tables.rs b/lib/cretonne/src/isa/enc_tables.rs
index dd4e67875f..71a3eba2e0 100644
--- a/lib/cretonne/src/isa/enc_tables.rs
+++ b/lib/cretonne/src/isa/enc_tables.rs
@@ -84,7 +84,11 @@ pub fn lookup_enclist<OffT1, OffT2>(ctrl_typevar: Type,
 {
     // TODO: The choice of legalization actions here is naive. This needs to be configurable.
     probe(level1_table, ctrl_typevar, ctrl_typevar.index())
-        .ok_or(Legalize::Narrow)
+        .ok_or_else(|| if ctrl_typevar.lane_type().bits() > 32 {
+                        Legalize::Narrow
+                    } else {
+                        Legalize::Expand
+                    })
         .and_then(|l1idx| {
             let l1ent = &level1_table[l1idx];
             let l2off = l1ent.offset.into() as usize;