aarch64: Add adcs instruction encodings

cranelift/codegen/src/isa/aarch64/inst/emit.rs

@@ -599,6 +599,8 @@ impl MachInstEmit for Inst {
                     ALUOp::Add64 => 0b10001011_000,
                     ALUOp::Adc32 => 0b00011010_000,
                     ALUOp::Adc64 => 0b10011010_000,
+                    ALUOp::AdcS32 => 0b00111010_000,
+                    ALUOp::AdcS64 => 0b10111010_000,
                     ALUOp::Sub32 => 0b01001011_000,
                     ALUOp::Sub64 => 0b11001011_000,
                     ALUOp::Sbc32 => 0b01011010_000,

cranelift/codegen/src/isa/aarch64/inst/emit_tests.rs

@@ -70,6 +70,26 @@ fn test_aarch64_binemit() {
         "A400069A",
         "adc x4, x5, x6",
     ));
+    insns.push((
+        Inst::AluRRR {
+            alu_op: ALUOp::AdcS32,
+            rd: writable_xreg(1),
+            rn: xreg(2),
+            rm: xreg(3),
+        },
+        "4100033A",
+        "adcs w1, w2, w3",
+    ));
+    insns.push((
+        Inst::AluRRR {
+            alu_op: ALUOp::AdcS64,
+            rd: writable_xreg(4),
+            rn: xreg(5),
+            rm: xreg(6),
+        },
+        "A40006BA",
+        "adcs x4, x5, x6",
+    ));
     insns.push((
         Inst::AluRRR {
             alu_op: ALUOp::Sub32,

cranelift/codegen/src/isa/aarch64/inst/mod.rs

@@ -87,6 +87,9 @@ pub enum ALUOp {
     /// Add with carry
     Adc32,
     Adc64,
+    /// Add with carry, settings flags
+    AdcS32,
+    AdcS64,
     /// Subtract with carry
     Sbc32,
     Sbc64,
@@ -3212,6 +3215,8 @@ impl Inst {
                 ALUOp::Lsl64 => ("lsl", OperandSize::Size64),
                 ALUOp::Adc32 => ("adc", OperandSize::Size32),
                 ALUOp::Adc64 => ("adc", OperandSize::Size64),
+                ALUOp::AdcS32 => ("adcs", OperandSize::Size32),
+                ALUOp::AdcS64 => ("adcs", OperandSize::Size64),
                 ALUOp::Sbc32 => ("sbc", OperandSize::Size32),
                 ALUOp::Sbc64 => ("sbc", OperandSize::Size64),
             }