aarch64: Add adcs instruction encodings

2021-06-08 12:42:38 +01:00
parent 59ebe4fa57
commit 61f07d79a7
3 changed files with 27 additions and 0 deletions
--- a/cranelift/codegen/src/isa/aarch64/inst/emit_tests.rs
+++ b/cranelift/codegen/src/isa/aarch64/inst/emit_tests.rs
@@ -70,6 +70,26 @@ fn test_aarch64_binemit() {
        "A400069A",
        "adc x4, x5, x6",
    ));
+    insns.push((
+        Inst::AluRRR {
+            alu_op: ALUOp::AdcS32,
+            rd: writable_xreg(1),
+            rn: xreg(2),
+            rm: xreg(3),
+        },
+        "4100033A",
+        "adcs w1, w2, w3",
+    ));
+    insns.push((
+        Inst::AluRRR {
+            alu_op: ALUOp::AdcS64,
+            rd: writable_xreg(4),
+            rn: xreg(5),
+            rm: xreg(6),
+        },
+        "A40006BA",
+        "adcs x4, x5, x6",
+    ));
    insns.push((
        Inst::AluRRR {
            alu_op: ALUOp::Sub32,