Lint fixes (#99)

* Replace a single-character string literal with a character literal.

* Use is_some() instead of comparing with Some(_).

* Add code-quotes around type names in comments.

* Use !...is_empty() instead of len() != 0.

* Tidy up redundant returns.

* Remove redundant .clone() calls.

* Remove unnecessary explicit lifetime parameters.

* Tidy up unnecessary '&'s.

* Add parens to make operator precedence explicit.

* Use debug_assert_eq instead of debug_assert with ==.

* Replace a &Vec argument with a &[...].

* Replace `a = a op b` with `a op= b`.

* Avoid unnecessary closures.

* Avoid .iter() and .iter_mut() for iterating over containers.

* Remove unneeded qualification.

lib/cretonne/src/regalloc/allocatable_set.rs

@@ -50,14 +50,14 @@ impl AllocatableSet {
     /// It is an error to take a register that doesn't have all of its register units available.
     pub fn take(&mut self, rc: RegClass, reg: RegUnit) {
         let (idx, bits) = bitmask(rc, reg);
-        debug_assert!((self.avail[idx] & bits) == bits, "Not available");
+        debug_assert_eq!(self.avail[idx] & bits, bits, "Not available");
         self.avail[idx] &= !bits;
     }
 
     /// Make `reg` available for allocation again.
     pub fn free(&mut self, rc: RegClass, reg: RegUnit) {
         let (idx, bits) = bitmask(rc, reg);
-        debug_assert!((self.avail[idx] & bits) == 0, "Not allocated");
+        debug_assert_eq!(self.avail[idx] & bits, 0, "Not allocated");
         self.avail[idx] |= bits;
     }
 
@@ -118,7 +118,7 @@ impl Iterator for RegSetIter {
                 let unit = unit_offset + word.trailing_zeros() as RegUnit;
 
                 // Clear that lowest bit so we won't find it again.
-                *word = *word & (*word - 1);
+                *word &= *word - 1;
 
                 return Some(unit);
             }

lib/cretonne/src/regalloc/pressure.rs

@@ -199,7 +199,7 @@ impl Pressure {
 
     /// Reset all counts to 0, both base and transient.
     pub fn reset(&mut self) {
-        for e in self.toprc.iter_mut() {
+        for e in &mut self.toprc {
             e.base_count = 0;
             e.transient_count = 0;
         }
@@ -220,7 +220,7 @@ impl Pressure {
 
     /// Reset all transient counts to 0.
     pub fn reset_transient(&mut self) {
-        for e in self.toprc.iter_mut() {
+        for e in &mut self.toprc {
             e.transient_count = 0;
         }
     }

lib/cretonne/src/regalloc/reload.rs

@@ -233,7 +233,7 @@ impl<'a> Context<'a> {
             // Create a live range for the new reload.
             let affinity = Affinity::Reg(cand.regclass.into());
             self.liveness.create_dead(reg, dfg.value_def(reg), affinity);
-            self.liveness.extend_locally(reg, ebb, inst, &pos.layout);
+            self.liveness.extend_locally(reg, ebb, inst, pos.layout);
         }
 
         // Rewrite arguments.

lib/cretonne/src/regalloc/spilling.rs

@@ -226,7 +226,7 @@ impl<'a> Context<'a> {
                 // Add register def to pressure, spill if needed.
                 while let Err(mask) = self.pressure.take_transient(op.regclass) {
                     dbg!("Need {} reg from {} throughs", op.regclass, throughs.len());
-                    self.spill_from(mask, throughs, dfg, &pos.layout);
+                    self.spill_from(mask, throughs, dfg, pos.layout);
                 }
             }
         }