Add a TargetIsa::allocatable_registers() method.

This gives the target ISA a chance to reserve registers like the stack
pointer or hard-wired 0 registers like %x0 on RISC-V.

lib/cretonne/src/isa/intel/abi.rs

@@ -2,6 +2,7 @@
 
 use ir;
 use isa::RegClass;
+use regalloc::AllocatableSet;
 use settings as shared_settings;
 use super::registers::{GPR, FPR};
 
@@ -16,3 +17,8 @@ pub fn legalize_signature(_sig: &mut ir::Signature,
 pub fn regclass_for_abi_type(ty: ir::Type) -> RegClass {
     if ty.is_int() { GPR } else { FPR }
 }
+
+/// Get the set of allocatable registers for `func`.
+pub fn allocatable_registers(_func: &ir::Function) -> AllocatableSet {
+    unimplemented!()
+}

lib/cretonne/src/isa/intel/mod.rs

@@ -12,6 +12,7 @@ use isa::enc_tables::{self as shared_enc_tables, lookup_enclist, general_encodin
 use isa::Builder as IsaBuilder;
 use isa::{TargetIsa, RegInfo, RegClass, EncInfo, Encoding, Legalize};
 use ir;
+use regalloc;
 
 #[allow(dead_code)]
 struct Isa {
@@ -86,6 +87,10 @@ impl TargetIsa for Isa {
         abi::regclass_for_abi_type(ty)
     }
 
+    fn allocatable_registers(&self, func: &ir::Function) -> regalloc::AllocatableSet {
+        abi::allocatable_registers(func)
+    }
+
     fn emit_inst(&self, func: &ir::Function, inst: ir::Inst, sink: &mut CodeSink) {
         binemit::emit_inst(func, inst, sink)
     }