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Fix legalization of SIMD fneg (#1286)

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Previously `fsub` was used but this fails when negating -0.0 and +0.0 in the SIMD spec tests; using more instructions, this change uses shifts to create a constant for flipping the most significant bit of each lane with `bxor`.
This commit is contained in:
Andrew Brown
2019-12-16 10:32:08 -08:00
committed by GitHub
parent 0604ec480c
commit 6181f20326
3 changed files with 32 additions and 6 deletions
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12
cranelift/filetests/filetests/isa/x86/simd-arithmetic-legalize.clif
View File

@@ -39,13 +39,17 @@ function %fneg_legalized() {
ebb0:
v0 = vconst.f32x4 [0x1.0 0x2.0 0x3.0 0x4.0]
v1 = fneg v0
; check: v4 = vconst.f32x4 0x00
; nextln: v1 = fsub v4, v0
; check: v4 = vconst.i32x4 0xffffffffffffffffffffffffffffffff
; nextln: v5 = ishl_imm v4, 31
; nextln: v6 = raw_bitcast.f32x4 v5
; nextln: v1 = bxor v0, v6
v2 = vconst.f64x2 [0x1.0 0x2.0]
v3 = fneg v2
; check: v5 = vconst.f64x2 0x00
; nextln: v3 = fsub v5, v2
; check: v7 = vconst.i64x2 0xffffffffffffffffffffffffffffffff
; nextln: v8 = ishl_imm v7, 63
; nextln: v9 = raw_bitcast.f64x2 v8
; nextln: v3 = bxor v2, v9
return
}

13
cranelift/filetests/filetests/isa/x86/simd-arithmetic-run.clif
View File

@@ -240,6 +240,19 @@ ebb0:
}
; run
function %fneg_f32x4() -> b1 {
ebb0:
v0 = vconst.f32x4 [0x0.0 -0x0.0 -Inf Inf]
v1 = fneg v0
v2 = vconst.f32x4 [-0x0.0 0x0.0 Inf -Inf]
v3 = fcmp eq v1, v2
v4 = vall_true v3
return v4
}
; run
function %fabs_f32x4() -> b1 {
ebb0:
v0 = vconst.f32x4 [0x0.0 -0x1.0 0x2.0 -0x3.0]