From 60e70da0e69060b6063cd6cd4ae9f245030e362a Mon Sep 17 00:00:00 2001 From: Jakob Stoklund Olesen Date: Tue, 13 Feb 2018 10:37:26 -0800 Subject: [PATCH] Add Intel encodings for ifcmp_imm. The instruction set has variants with 8-bit and 32-bit signed immediate operands. Add a TODO to use a TEST instruction for the special case ifcmp_imm x, 0. --- cranelift/filetests/isa/intel/binary32.cton | 10 ++++++++++ cranelift/filetests/isa/intel/binary64.cton | 20 +++++++++++++++++++ lib/cretonne/meta/isa/intel/encodings.py | 3 +++ lib/cretonne/meta/isa/intel/recipes.py | 22 +++++++++++++++++++++ 4 files changed, 55 insertions(+) diff --git a/cranelift/filetests/isa/intel/binary32.cton b/cranelift/filetests/isa/intel/binary32.cton index e507e5fbcd..ea9613f9fa 100644 --- a/cranelift/filetests/isa/intel/binary32.cton +++ b/cranelift/filetests/isa/intel/binary32.cton @@ -540,5 +540,15 @@ ebb1: ; asm: cmpl %esp, %esi [-,%eflags] v41 = ifcmp_sp v2 ; bin: 39 e6 + ; asm: cmpl $-100, %ecx + [-,%eflags] v42 = ifcmp_imm v1, -100 ; bin: 83 f9 9c + ; asm: cmpl $100, %esi + [-,%eflags] v43 = ifcmp_imm v2, 100 ; bin: 83 fe 64 + + ; asm: cmpl $-10000, %ecx + [-,%eflags] v44 = ifcmp_imm v1, -10000 ; bin: 81 f9 ffffd8f0 + ; asm: cmpl $10000, %esi + [-,%eflags] v45 = ifcmp_imm v2, 10000 ; bin: 81 fe 00002710 + return } diff --git a/cranelift/filetests/isa/intel/binary64.cton b/cranelift/filetests/isa/intel/binary64.cton index 486223ec6f..59c5f0b2f0 100644 --- a/cranelift/filetests/isa/intel/binary64.cton +++ b/cranelift/filetests/isa/intel/binary64.cton @@ -621,6 +621,16 @@ ebb1: ; asm: cmpq %rsp, %r10 [-,%eflags] v41 = ifcmp_sp v2 ; bin: 49 39 e2 + ; asm: cmpq $-100, %rcx + [-,%eflags] v522 = ifcmp_imm v1, -100 ; bin: 48 83 f9 9c + ; asm: cmpq $100, %r10 + [-,%eflags] v523 = ifcmp_imm v2, 100 ; bin: 49 83 fa 64 + + ; asm: cmpq $-10000, %rcx + [-,%eflags] v524 = ifcmp_imm v1, -10000 ; bin: 48 81 f9 ffffd8f0 + ; asm: cmpq $10000, %r10 + [-,%eflags] v525 = ifcmp_imm v2, 10000 ; bin: 49 81 fa 00002710 + return } @@ -994,6 +1004,16 @@ ebb0: ; asm: cmpl %r10d, %esi [-,%eflags] v521 = ifcmp v2, v3 ; bin: 44 39 d6 + ; asm: cmpl $-100, %ecx + [-,%eflags] v522 = ifcmp_imm v1, -100 ; bin: 83 f9 9c + ; asm: cmpl $100, %r10d + [-,%eflags] v523 = ifcmp_imm v3, 100 ; bin: 41 83 fa 64 + + ; asm: cmpl $-10000, %ecx + [-,%eflags] v524 = ifcmp_imm v1, -10000 ; bin: 81 f9 ffffd8f0 + ; asm: cmpl $10000, %r10d + [-,%eflags] v525 = ifcmp_imm v3, 10000 ; bin: 41 81 fa 00002710 + ; asm: testl %ecx, %ecx ; asm: je ebb1x brz v1, ebb1 ; bin: 85 c9 74 18 diff --git a/lib/cretonne/meta/isa/intel/encodings.py b/lib/cretonne/meta/isa/intel/encodings.py index 449e159f71..1e1eff820c 100644 --- a/lib/cretonne/meta/isa/intel/encodings.py +++ b/lib/cretonne/meta/isa/intel/encodings.py @@ -363,6 +363,9 @@ I64.enc(base.trapif, r.trapif, 0) # enc_i32_i64(base.icmp, r.icscc, 0x39) enc_i32_i64(base.ifcmp, r.rcmp, 0x39) +enc_i32_i64(base.ifcmp_imm, r.rcmpib, 0x83, rrr=7) +enc_i32_i64(base.ifcmp_imm, r.rcmpid, 0x81, rrr=7) +# TODO: We could special-case ifcmp_imm(x, 0) to TEST(x, x). I32.enc(base.ifcmp_sp.i32, *r.rcmp_sp(0x39)) I64.enc(base.ifcmp_sp.i64, *r.rcmp_sp.rex(0x39, w=1)) diff --git a/lib/cretonne/meta/isa/intel/recipes.py b/lib/cretonne/meta/isa/intel/recipes.py index 56f67306cb..9696a7ed43 100644 --- a/lib/cretonne/meta/isa/intel/recipes.py +++ b/lib/cretonne/meta/isa/intel/recipes.py @@ -1081,6 +1081,28 @@ fcmp = TailRecipe( modrm_rr(in_reg1, in_reg0, sink); ''') +# XX /n, MI form with imm8. +rcmpib = TailRecipe( + 'rcmpib', BinaryImm, size=2, ins=GPR, outs=FLAG.eflags, + instp=IsSignedInt(BinaryImm.imm, 8), + emit=''' + PUT_OP(bits, rex1(in_reg0), sink); + modrm_r_bits(in_reg0, bits, sink); + let imm: i64 = imm.into(); + sink.put1(imm as u8); + ''') + +# XX /n, MI form with imm32. +rcmpid = TailRecipe( + 'rcmpid', BinaryImm, size=5, ins=GPR, outs=FLAG.eflags, + instp=IsSignedInt(BinaryImm.imm, 32), + emit=''' + PUT_OP(bits, rex1(in_reg0), sink); + modrm_r_bits(in_reg0, bits, sink); + let imm: i64 = imm.into(); + sink.put4(imm as u32); + ''') + # Same as rcmp, but second operand is the stack pointer. rcmp_sp = TailRecipe( 'rcmp_sp', Unary, size=1, ins=GPR, outs=FLAG.eflags,