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Apply conditional compilation of isa targets

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This commit is contained in:
Aleksey Kuznetsov
2017-07-29 20:05:45 +05:00
committed by Jakob Stoklund Olesen
parent c057e005ce
commit 5fa991e325
4 changed files with 55 additions and 28 deletions
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3
lib/cretonne/src/regalloc/pressure.rs
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@@ -247,6 +247,7 @@ impl fmt::Display for Pressure {
}
#[cfg(test)]
#[cfg(build_arm32)]
mod tests {
use isa::{TargetIsa, RegClass};
use regalloc::AllocatableSet;
@@ -261,7 +262,7 @@ mod tests {
let shared_builder = settings::builder();
let shared_flags = settings::Flags::new(&shared_builder);
isa::lookup("arm32").map(|b| b.finish(shared_flags))
isa::lookup("arm32").ok().map(|b| b.finish(shared_flags))
}
// Get a register class by name.

3
lib/cretonne/src/regalloc/solver.rs
View File

@@ -700,6 +700,7 @@ impl Solver {
}
#[cfg(test)]
#[cfg(build_arm32)]
mod tests {
use entity_ref::EntityRef;
use ir::Value;
@@ -716,7 +717,7 @@ mod tests {
let shared_builder = settings::builder();
let shared_flags = settings::Flags::new(&shared_builder);
isa::lookup("arm32").map(|b| b.finish(shared_flags))
isa::lookup("arm32").ok().map(|b| b.finish(shared_flags))
}
// Get a register class by name.