Split out instruction definitions.

- cdsl.instructions defines the Instruction class.
- base.instructions defines the base instruction set.

lib/cretonne/meta/isa/riscv/defs.py

@@ -5,9 +5,9 @@ Commonly used definitions.
 """
 from __future__ import absolute_import
 from cretonne import TargetISA, CPUMode
-import cretonne.base
+import base.instructions
 
-isa = TargetISA('riscv', [cretonne.base.instructions])
+isa = TargetISA('riscv', [base.instructions.GROUP])
 
 # CPU modes for 32-bit and 64-bit operation.
 RV32 = CPUMode('RV32', isa)

lib/cretonne/meta/isa/riscv/encodings.py

@@ -2,7 +2,7 @@
 RISC-V Encodings.
 """
 from __future__ import absolute_import
-from cretonne import base
+from base import instructions as base
 from .defs import RV32, RV64
 from .recipes import OPIMM, OPIMM32, OP, OP32, R, Rshamt, I
 from .settings import use_m